Wafer level chip size packaged chip device with a double-layer lead structure and method of fabricating the same

• US 7,663,213 B2
• Filed: 11/13/2006
• Issued: 02/16/2010
• Est. Priority Date: 11/13/2006
• Status: Active Grant

• Current Assignee: China Wafer Level CSP Co., Ltd.
• Original Assignee: China Wafer Level CSP Co., Ltd.
• Inventors: Wang, Youjun, Wang, Qingwei, Wang, Wei, Xu, Qinqin, Yu, Guoqing
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US11/559,157
• Publication Number:
  US 20080111223A1
• Time in Patent Office: 1,191 Days
• Field of Search: 257/678, 257/701, 257/690, 257/E21.499, 257/E23.18, 438/106, 438/123
• US Class Current: 257/678
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention disclosed a wafer level chip size packaged chip device with a double-layer lead structure and methods of fabricating the same. The double-layer lead is designed to meet a tendency of increasing quantity per area of peripheral arrayed compatible pads on a semiconductor chip, and also to save more space for layout of lead on the chip bottom surface for avoiding potential short inbetween which happen in increasing probability with increasing quantity per area on the condition of one-layer lead.

Claims

1. A wafer level chip size packaged chip device with a double-layer lead structure comprising:

a substrate having formed thereon a silicon chip, with plurality of compatible pads disposed at the periphery of said chip on said substrate;

a first glass disposed above said chip and said substrate;

a layer of insulating material disposed at the back of said substrate;

a first metal layer disposed at the back of said layer of insulating material, with a through hole at the center of said first metal layer;

a first solder mask disposed at the back of said first metal layer, with at least one opening on said first solder mask so as to enable part of said first metal layer exposed through said opening of said first solder mask;

a second metal layer disposed at the sides of said chip device and on the back of said first solder mask;

plurality of solder bumps each attached to a bottom end of said second metal layer so as to enable electrical connection between said compatible pads and said solder bumps via said second metal layer and said first metal layer,

wherein, said packaged chip device has T-shape junction between said compatible pads and said second metal layer, and has L-shape and U-shape junction between said first metal layer and said second metal layer, such that, each of said compatible pads and said solder bumps are electrically connected via T-, L-, U-shape junctions.

3. A wafer level chip size packaged chip device with a double-layer lead structure double-layer lead package structure as claimed in claim 1, wherein a cavity is formed between said substrate and said first glass so as to receive therein said chip on said substrate.

4. A wafer level chip size packaged chip device with a double-layer lead structure double-layer lead package structure as claimed in claim 1, wherein a second glass is disposed between said layer of insulating material and said first metal layer.

5. A wafer level chip size packaged chip device with a double-layer lead structure double-layer lead package structure as claimed in claim 1, wherein a third solder mask is disposed between said second glass and said first metal layer.

2. A wafer level chip size packaged chip device with a double-layer lead structure comprising:

a substrate having formed thereon a silicon chip, with plurality of compatible pads disposed at the periphery of said chip on said substrate;

a first glass disposed above said chip and said substrate;

a layer of insulating material disposed at the back of said substrate;

a first metal layer disposed at the back of said layer of insulating material, with a through hole at the center of said first metal layer;

a first solder mask disposed at the back of said first metal layer, with at least one opening on said first solder mask so as to enable part of said first metal layer exposed through said opening of said first solder mask;

a second metal layer disposed at the sides of said chip device and on the back of said first solder mask;

plurality of solder bumps each attached to a bottom end of said second metal layer so as to enable electrical connection between said compatible pads and said solder bumps via said second metal layer and said first metal layer,

wherein said packaged chip device has T-shape junction between said compatible pads and said second metal layer, and has T-shape and 2U-shape junctions between said first metal layer and said second metal layer, such that, each of said compatible pads and said solder bumps are electrically connected via 2T-, 2U-shape junctions.

6. A wafer level chip size packaged chip device with a double-layer lead structure double-layer lead package structure as claimed in claim 2, wherein a cavity is formed between said substrate and said first glass so as to receive therein said chip on said substrate.

7. A wafer level chip size packaged chip device with a double-layer lead structure double-layer lead package structure as claimed in claim 2, wherein a second glass is disposed between said layer of insulating material and said first metal layer.