Image sensor module with a three-dimensional die-stacking structure

• US 7,663,231 B2
• Filed: 01/28/2008
• Issued: 02/16/2010
• Est. Priority Date: 06/13/2007
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Chiang, Chia-Wen, Kuo, Tzu-Ying, Chang, Hsiang-Hung, Chang, Shu-Ming
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US12/010,617
• Publication Number:
  US 20080308928A1
• Time in Patent Office: 750 Days
• Field of Search: 257/724, 257/725, 257/E23.124, 257/E23.145
• US Class Current: 257/724
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/051 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 27/14618 : Containers
• CPC Class Codes: H01L 27/14634 : Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip

Abstract

This invention provides an image sensor module with a three-dimensional die-stacking structure. By filling a conductive material into through silicon vias within at least one image sensor die, and into via holes within an insulating layer, vertical electrical connections are formed between the image sensor die and an image processor buried in the insulating layer. A plurality of solder bumps is formed on a backside of the image sensor module so that the module can be directly assembled onto a circuit board. The image sensor module of this invention is characterized by a wafer-level packaging architecture and a three-dimensional die-stacking structure, which reduces electrical connection lengths within the module and thus reduces an area and height of the whole packaged module.

Claims

1. An image sensor module with a three-dimensional die-stacking structure, comprising:

at least one image sensor die;

at least one image processor die, said image processor die and said image sensor die being stacked and jointed to each other, wherein a sensing surface of said image sensor die faces up, and said image sensor die is provided with a plurality of vertical electrical conductive wires passing therethrough;

an optically transparent substrate formed on said sensing surface of said image sensor die;

an insulating layer in which said image processor die is buried and said electrical conductive wires pass therethrough so that vertical and horizontal electrical connections between said image sensor die and said image processor die are established; and

a plurality of electrical conductive pads formed on a backside of said image sensor module.

2. The image sensor module with a three-dimensional die-stacking structure of claim 1, wherein a backside of said image sensor die has a slot for placing said image processor die.

3. The image sensor module with a three-dimensional die-stacking structure of claim 1, wherein said image processor die is stacked under said image sensor die in a manner of a front side of said image processor die facing up or facing down.

4. The image sensor module with a three-dimensional die-stacking structure of claim 1, wherein the horizontal electrical connections are established between said image processor die and said electrical conductive pads, or between said image processor die and said image sensor die.

5. The image sensor module with a three-dimensional die-stacking structure of claim 1, wherein at least one of said vertical electrical conductive wires passes through said image sensor die and said image processor die.

6. The image sensor module with a three-dimensional die-stacking structure of claim 5, wherein the horizontal electrical connections are established between said image processor die and said electrical conductive pads, or between said image processor die and said image sensor die.

7. The image sensor module with a three-dimensional die-stacking structure of claim 5, wherein said image processor die is stacked under said image sensor die in a manner of a front side of said image processor die facing up or facing down.

8. The image sensor module with a three-dimensional die-stacking structure of claim 1, further comprising an adhesive layer to joint said image sensor die and said image processor die.

9. The image sensor module with a three-dimensional die-stacking structure of claim 1, further comprising a plurality of solder bumps respectively formed under one of said electrical conductive pads corresponding thereto, wherein electrical connections between said image sensor module and the external are established through said solder bumps.