Scannable dynamic circuit latch

• US 7,663,408 B2
• Filed: 06/30/2005
• Issued: 02/16/2010
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Kottapalli, Venkata, Sousa, Jose, Masleid, Robert Paul
• Primary Examiner(s): Tan; Vibol
• Assistant Examiner(s): Tabler; Matthew C
• Application Number:
  US11/171,695
• Publication Number:
  US 20070008012A1
• Time in Patent Office: 1,692 Days
• Field of Search: 326/121, 326 56- 58
• US Class Current: 326/112
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

A dynamic circuit latch, having the functionality of a domino circuit and a transparent latch, without the delay associated with the inclusion of a separate series latch element. Embodiments include a fast scannable footed Domino dyanmic latch. Also described is a fast scannable delay reset Domino dynamic latch. A fast scannable compound Domino dynamic latch is also described.

Claims

1. A dynamic circuit latch comprising:

a domino component, for receiving a clock signal and an input signal, and for producing an output signal; and

a state component, coupled to the domino component, for retaining the output signal, wherein an output of said state component is coupled to an output of said domino component, comprising;

a first tri-state buffer, wherein the first tri-state buffer is coupled to a first scan clock signal;

a second tri-state buffer coupled to the first tri-state buffer, wherein the second tri-state buffer is coupled to the clock signal, and wherein the domino component and the state component are configured to assume a tri-state when induced by the clock signal, such that the output signal is held at the state component, and wherein the input signal cannot alter the output signal while so held, and wherein the first tri-state buffer and the second tri-state buffer are configured to function as an exposed, scannable latch when the domino component is in the tri-state, and wherein the first scan clock signal and the clock signal are separate clock signals; and

a slave latch configured for monitoring the output signal, wherein the slave latch is coupled to a second scan clock signal.

2. The dynamic circuit latch of claim 1 free of the delay imposed by inclusion of a separate series latch circuit.

3. The dynamic circuit latch of claim 1, wherein the slave latch is coupled to the second tri-state buffer.

4. The dynamic circuit latch of claim 1, wherein the domino

component comprises:

a precharge component, for precharging the domino component;

a function component, coupled to the precharge component, for performing a function with the input signal and producing the output signal;

a keeper component, coupled to the precharge component, for holding the output signal from the function component; and

an output component, coupled to the precharge component, for holding the output signal.

5. The dynamic circuit latch of claim 4, wherein the domino component further comprises:

a foot component, coupled to the precharge component, for cutting off the input signal when induced by the clock signal.

6. The dynamic circuit latch of claim 1, wherein the domino component comprises:

a plurality of precharge components;

a plurality of function components, coupled to the plurality of precharge components, for performing a plurality of functions and producing a plurality of output signals;

a plurality of keeper components, coupled to the plurality of precharge components, for holding the plurality of outputs signals; and

an output component, coupled to the plurality of precharge components, for holding the output signal.

7. A scannable latch circuit comprising:

a domino circuit comprising a data input port for receiving an input data signal and a clock input port for receiving a clock input wherein the domino circuit is configured to generate an output signal over an output port; and

a scannable state component coupled to the output port, comprising;

a first tri-state buffer circuit coupled to a scan-in port, coupled to the output port, and coupled to a first scan clock input;

a second tri-state buffer circuit coupled to the first tri-state buffer circuit and coupled to the output port, and coupled to the clock input, wherein the first scan clock input and the clock input are coupled to separate clock inputs; and

a scan-out read circuit coupled to the second tri-state buffer circuit, a scan-out port, and a second scan clock input;

wherein the scannable state component, in a first clock mode, is configured to hold a signal state of the output port and, wherein further, signal transitions at the data input port do not alter the signal state.

8. The scannable latch circuit as described in claim 7 wherein the scannable state component comprises a scan-in port and a scan-out port.

9. The scannable latch circuit as described in claim 7 wherein the domino circuit comprises a footed domino circuit.

10. The scannable latch circuit as described in claim 7 wherein the domino circuit comprises a delay reset domino circuit.

11. The scannable latch circuit as described in claim 7 wherein the domino circuit comprises a compound domino circuit.

12. The scannable latch circuit as described in claim 7 wherein the domino circuit further comprises:

a precharge subcircuit;

a keeper subcircuit coupled to the precharge subcircuit; and

an output buffer subcircuit coupled to the keeper subcircuit and coupled to the precharge subcircuit wherein the output buffer subcircuit is for generating the output signal.

13. A dynamic circuit latch, comprising:

a domino component coupled to a clock port to receive a clock signal and an input port to receive an input signal, wherein the domino component is configured in a first clock state to produce an output at an output port, and wherein the domino component is configured in a second clock state to prevent the input from affecting the output; and

a state component coupled to the output port, comprising;

a first tri-state buffer circuit coupled to the scan-in port, coupled to a scan-clock input port, and coupled to a first scan clock signal; and

a second tri-state buffer circuit coupled to the first tri-state buffer, coupled to a functional clock input port to receive the clock signal, coupled to a second scan clock signal, and coupled to the clock signal wherein the first scan clock signal and the clock signal are separate clock signals,

wherein the state component is configured in the first clock state to inhibit conduction through the state component, and wherein the state component is configured in the second clock state to hold the output.

14. The dynamic circuit latch of claim 13 wherein the domino component comprises a footed domino circuit.

15. The dynamic circuit latch of claim 13 wherein the domino circuit comprises a delay reset domino circuit.

16. The dynamic circuit latch of claim 13 wherein the domino circuit comprises a compound domino circuit.

17. The dynamic circuit latch of claim 16 wherein the compound domino circuit comprises a footed compound domino circuit.

18. The dynamic circuit latch of claim 16 wherein the compound domino circuit comprises a delay reset compound domino circuit.

19. The dynamic circuit latch of claim 13 wherein the state element comprises:

a scan-in read circuit coupled to a scan-in port and coupled to the output port; and

a scan-out read circuit coupled to the scan-in read circuit and coupled to a scan-out port for outputting a held value.

20. The dynamic circuit latch of claim 13 wherein the state element further comprises:

a scan-out read circuit coupled to the second tri-state buffer circuit and coupled to the scan-out port.

21. The dynamic circuit latch of claim 13 wherein the domino component farther comprises:

a precharge subcircuit;

a keeper subcircuit coupled to the precharge subcircuit; and

an output buffer subcircuit coupled to the keeper subcircuit and coupled to the precharge subcircuit wherein the output buffer subcircuit is for generating the output signal.

22. The dynamic circuit latch of claim 21 wherein the first tri-state buffer circuit is coupled to the output port and wherein the second tri-state buffer circuit is coupled to the output port and further comprises:

a scan-out read circuit coupled to the second tri-state buffer circuit and coupled to a scan-out port.

23. The dynamic circuit latch of claim 16 wherein the compound domino component comprises a plurality of functional units each coupled to a plurality of half keeper circuits, wherein each functional unit has a separate input.

24. A dynamic circuit latch comprising:

domino means for producing an output signal, wherein the domino means is configured to receive a clock signal and an input signal; and

state means for retaining the output signal, wherein an output of the state means is coupled to an output of the domino means and wherein the domino means and the state means are configured to assume a tri-state when induced by the clock signal, such that the output signal is held at the state means, and wherein the input signal cannot alter the output signal while so held, the state means comprising;

first tri-state buffer means, wherein the first tri-state buffer means is coupled to a first scan clock signal; and

second tri-state buffer means coupled to the first tri-state buffer means and coupled to a second scan clock signal, wherein the second tri-state buffer means is coupled to the clock signal, and wherein the first tri-state buffer means and the second tri-state buffer means are configured to function as an exposed, scannable latch when the domino means is in the tri-state, and wherein the first scan clock signal and the clock signal are separate clock signals.

25. The dynamic circuit latch of claim 24 free of the delay imposed by inclusion of a separate series latch circuit.

26. The dynamic circuit latch of claim 24, further comprising:

slave latch means for allowing monitoring of the output signal, coupled to the second tri-state buffer means.

27. The dynamic circuit latch of claim 24, wherein the domino means comprises:

means for precharging the domino means;

means for performing a function with the input signal and producing the output signal, coupled to the means for precharging;

means for holding the output signal the means for performing a function, coupled to the means for precharging; and

means for holding the output signal, coupled to the means for precharging.

28. The dynamic circuit latch of claim 27, wherein the domino means further comprises:

means for cutting off the input signal when induced by the clock signal, coupled to the means for precharging.

29. The dynamic circuit latch of claim 27, wherein the means for precharging comprises a plurality of precharge components, wherein the means for performing a function with the input signal and producing the output signal comprises a plurality of function components, coupled to the plurality of precharge components, for performing a plurality of functions and producing a plurality of output signals, and wherein the means for holding the output signal comprises a plurality of keeper components, coupled to the plurality of precharge components, for holding the plurality of output signals, wherein the means for holding the output signal is coupled to the plurality of precharge components.