Oscillator circuit having a stable output signal resistant to power supply voltage fluctuation

• US 7,663,447 B2
• Filed: 10/19/2007
• Issued: 02/16/2010
• Est. Priority Date: 10/31/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Matsuzaki, Takanori
• Primary Examiner(s): Mis; David
• Application Number:
  US11/875,088
• Publication Number:
  US 20080258822A1
• Time in Patent Office: 851 Days
• Field of Search: 331/57, 331/175, 331/176, 331/177.R, 331/185, 331/186, 455/75, 455/76
• US Class Current: 331/186
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H03K 2005/00039 having four transistors serially
• CPC Class Codes: H03K 2005/0013 Avoiding variations of delay due to power supply
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A stable frequency is outputted by an oscillator circuit including a constant current circuit which is electrically connected between a first terminal and a second terminal, a voltage controlled oscillator circuit in which an oscillation frequency fluctuates in accordance with a potential difference between power supply voltage terminals, an n-channel transistor, a p-channel transistor in which a gate-source voltage is set to be constant by the constant current circuit, and a capacitor, in which a source electrode of the p-channel transistor is electrically connected to the first terminal, a drain electrode of the p-channel transistor is electrically connected a drain electrode and a gate electrode of the n-channel transistor, a source electrode of the n-channel transistor is electrically connected to the second terminal, and a gate electrode of the n-channel transistor is electrically connected to the second terminal through the capacitor.

Claims

1. A semiconductor device comprising:

a voltage controlled oscillator circuit having a first voltage terminal, a second voltage terminal and an output terminal configured to output a clock signal;

an antenna circuit configured to transmit and receive a signal;

a rectifier circuit configured to generate a power supply voltage between the first voltage terminal and the second voltage terminal from the signal;

a control circuit electrically connected between the first voltage terminal and the second voltage terminal, and configured so that a potential difference between the first voltage terminal and a control terminal of the control circuit remains constant;

a first transistor having;

a first gate electrode electrically connected to an input terminal of the voltage controlled oscillator circuit;

a first source region electrically connected to the second voltage terminal; and

a first drain region electrically connected to the first gate electrode; and

a second transistor having;

a second gate electrode electrically connected to the control terminal of the control circuit;

a second source region electrically connected to the first voltage terminal; and

a second drain region electrically connected to the first drain region.

2. The semiconductor device according to claim 1, further comprising a capacitor electrically connected between the first gate electrode and the first source region.

3. The semiconductor device according to claim 1, wherein the first transistor and the second transistor are thin film transistors formed over a substrate having an insulating surface.

4. The semiconductor device according to claim 1, further comprising:

a logic circuit configured to receive the clock signal and a data signal;

a memory control circuit configured to receive the data signal from the logic circuit; and

a memory circuit configured to be controlled by the memory control circuit.

5. A semiconductor device comprising:

a voltage controlled oscillator circuit having an input voltage terminal, a reference voltage terminal and an output terminal configured to output a clock signal;

an antenna circuit configured to transmit and receive a signal;

a rectifier circuit configured to generate a power supply voltage between the input voltage terminal and the reference voltage terminal from the signal;

a control circuit electrically connected between the input voltage terminal and the reference voltage terminal, and configured so that a potential difference between the input voltage terminal and a control terminal of the control circuit remains constant;

an n-channel transistor having;

a first gate electrode electrically connected to an input terminal of the voltage controlled oscillator circuit;

a first source region electrically connected to the reference voltage terminal; and

a first drain region electrically connected to the first gate electrode; and

a p-channel transistor having;

a second gate electrode electrically connected to the control terminal of the control circuit;

a second source region electrically connected to the input voltage terminal; and

a second drain region electrically connected to the first drain region.

6. The semiconductor device according to claim 5, further comprising a capacitor electrically connected between the first gate electrode and the first source region.

7. The semiconductor device according to claim 5, wherein the n-channel transistor and the p-channel transistor are thin film transistors formed over a substrate having an insulating surface.

8. The semiconductor device according to claim 5, further comprising:

a logic circuit configured to receive the clock signal and a data signal;

a memory control circuit configured to receive the data signal from the logic circuit; and

a memory circuit configured to be controlled by the memory control circuit.

9. A semiconductor device comprising:

a voltage controlled oscillator circuit having an input voltage terminal, a reference voltage terminal and an output terminal configured to output a clock signal;

an antenna circuit configured to transmit and receive a signal;

a rectifier circuit configured to generate a power supply voltage between the input voltage terminal and the reference voltage terminal from the signal;

a control circuit electrically connected between the input voltage terminal and the reference voltage terminal, and configured so that a potential difference between the reference voltage terminal and a control terminal of the control circuit remains constant;

a p-channel transistor having;

a first gate electrode electrically connected to an input terminal of the voltage controlled oscillator circuit;

a first source region electrically connected to the input voltage terminal; and

a first drain region electrically connected to the first gate electrode; and

an n-channel transistor having;

a second gate electrode electrically connected to the control terminal of the control circuit;

a second source region electrically connected to the reference voltage terminal; and

a second drain region electrically connected to the first drain region.

10. The semiconductor device according to claim 9, further comprising a capacitor electrically connected between the first gate electrode and the first source region.

11. The semiconductor device according to claim 9, wherein the n-channel transistor and the p-channel transistor are thin film transistors formed over a substrate having an insulating surface.

12. The semiconductor device according to claim 9, further comprising:

a logic circuit configured to receive the clock signal and a data signal;

a memory control circuit configured to receive the data signal from the logic circuit; and

a memory circuit configured to be controlled by the memory control circuit.

13. A semiconductor device comprising:

a voltage controlled oscillator circuit having an input voltage terminal, a reference voltage terminal and an output terminal configured to output a clock signal;

an antenna circuit configured to transmit and receive a signal;

a rectifier circuit configured to generate a power supply voltage between the input voltage terminal and the reference voltage terminal from the signal; and

a control circuit comprising;

a p-channel first control transistor having;

a first gate electrode electrically connected to a control terminal of the control circuit;

a first source region electrically connected to the input voltage terminal; and

a first drain region electrically connected to the control terminal of the control circuit;

a p-channel second control transistor having;

a second gate electrode electrically connected to the control terminal of the control circuit;

a second source region electrically connected to the input voltage terminal; and

a second drain region;

an n-channel third control transistor having;

a third gate electrode electrically connected to the second drain region;

a third source region; and

a third drain region electrically connected to the control terminal of the control circuit;

an n-channel fourth control transistor having;

a fourth gate electrode electrically connected to the third source region;

a fourth source region electrically connected to the reference voltage terminal; and

a fourth drain region electrically connected to the third gate electrode; and

a resistor electrically connected between the fourth gate electrode and the reference voltage terminal;

an n-channel fifth transistor having;

a fifth gate electrode electrically connected to an input terminal of the voltage controlled oscillator circuit;

a fifth source region electrically connected to the reference voltage terminal; and

a fifth drain region electrically connected to the fifth gate electrode; and

a p-channel sixth transistor having;

a sixth gate electrode electrically connected to the control terminal of the control circuit;

a sixth source region electrically connected to the input voltage terminal; and

a sixth drain region electrically connected to the fifth drain region.

14. The semiconductor device according to claim 13, further comprising a capacitor electrically connected between the fifth gate electrode and the fifth source region.

15. The semiconductor device according to claim 13, wherein the p-channel first control transistor, the p-channel second control transistor, the n-channel third control transistor, the n-channel fourth control transistor, the n-channel fifth transistor and the p-channel sixth transistor are thin film transistors formed over a substrate having an insulating surface.

16. The semiconductor device according to claim 13, further comprising:

a logic circuit configured to receive the clock signal and a data signal;

a memory control circuit configured to receive the data signal from the logic circuit; and

a memory circuit configured to be controlled by the memory control circuit.

17. A semiconductor device comprising:

a voltage controlled oscillator circuit having an input voltage terminal, a reference voltage terminal and an output terminal configured to output a clock signal;

an antenna circuit configured to transmit and receive a signal;

a rectifier circuit configured to generate a power supply voltage between the input voltage terminal and the reference voltage terminal from the signal; and

a control circuit comprising;

an n-channel first control transistor having;

a first gate electrode electrically connected to a control terminal of the control circuit;

a first source region electrically connected to the reference voltage terminal; and

a first drain region electrically connected to the control terminal of the control circuit;

an n-channel second control transistor having;

a second gate electrode electrically connected to the control terminal of the control circuit;

a second source region electrically connected to the reference voltage terminal; and

a second drain region;

a p-channel third control transistor having;

a third gate electrode electrically connected to the second drain region;

a third source region; and

a third drain region electrically connected to the control terminal of the control circuit;

a p-channel fourth control transistor having;

a fourth gate electrode electrically connected to the third source region;

a fourth source region electrically connected to the input voltage terminal; and

a fourth drain region electrically connected to the third gate electrode; and

a resistor electrically connected between the fourth gate electrode and the input voltage terminal;

a p-channel fifth transistor having;

a fifth gate electrode electrically connected to an input terminal of the voltage controlled oscillator circuit;

a fifth source region electrically connected to the input voltage terminal; and

a fifth drain region electrically connected to the fifth gate electrode; and

an n-channel sixth transistor having;

a sixth gate electrode electrically connected to the control terminal of the control circuit;

a sixth source region electrically connected to the reference voltage terminal; and

a sixth drain region electrically connected to the fifth drain region.

18. The semiconductor device according to claim 17, further comprising a capacitor electrically connected between the fifth gate electrode and the fifth source region.

19. The semiconductor device according to claim 17, wherein the n-channel first control transistor, the n-channel second control transistor, the p-channel third control transistor, the p-channel fourth control transistor, the p-channel fifth transistor and the n-channel sixth transistor are thin film transistors formed over a substrate having an insulating surface.

20. The semiconductor device according to claim 17, further comprising:

a logic circuit configured to receive the clock signal and a data signal;

a memory control circuit configured to receive the data signal from the logic circuit; and

a memory circuit configured to be controlled by the memory control circuit.