Sense amplifier circuit having current mirror architecture

• US 7,663,928 B2
• Filed: 10/09/2007
• Issued: 02/16/2010
• Est. Priority Date: 10/09/2007
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Lin, Ching-Yuan, Tsai, Hong-Ping
• Primary Examiner(s): Nguyen; Tuan T
• Assistant Examiner(s): REIDLINGER, RONALD LANCE
• Application Number:
  US11/868,965
• Publication Number:
  US 20090091995A1
• Time in Patent Office: 861 Days
• Field of Search: 365/185.21, 365/205, 365207-214, 365/189.05, 327 52- 55, 327/57
• US Class Current: 365/185.21
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

A sense amplifier circuit for use in a semiconductor memory device has complemented logic states at opposite sides of the latch circuit in the sense amplifier circuit determinate all the time in operation. The sense amplifier circuit takes advantage of a current mirror circuit for ascending or descending a voltage level at the gate of a transistor by charge accumulation or charge dissipation, which turns on or off the transistor so as to control the logic states at opposite sides of the latch circuit in the sense amplifier circuit.

Claims

1. A sense amplifier circuit for a semiconductor memory device, comprising:

a latch circuit having a first terminal and a second terminal;

a first transistor having a first terminal electrically connected to the first terminal of the latch circuit, a second terminal electrically connected to a low bias supply, and a gate;

a second transistor having a first terminal electrically connected to the second terminal of the latch circuit, a second terminal electrically connected to the low bias supply, and a gate for receiving a first control signal; and

a current mirror circuit having a first terminal for receiving a first current, a second terminal electrically connected to the gate of the first transistor, a third terminal electrically connected to the low bias supply, and a fourth terminal electrically connected to the low bias supply wherein the latch circuit comprises;

a first inverter having an input terminal electrically connected to he first terminal of the first transistor, and an output terminal electrically connected to the first terminal of the second transistor; and

a second inverter having an input terminal electrically connected to the first terminal of the second transistor, and an output terminal electrically connected to the first terminal of the first transistor.

2. The sense amplifier circuit of claim 1, wherein the first and second transistors are NMOS transistors.

3. The sense amplifier circuit of claim 1, wherein the current mirror circuit comprises:

a third transistor having a first terminal for receiving the first current, a gate electrically connected to the first terminal, and a second terminal electrically connected to the low bias supply; and

a fourth transistor having a gate electrically connected to the gate of the third transistor, a first terminal electrically connected to the gate of the first transistor, and a second terminal electrically connected to the low bias supply.

4. The sense amplifier circuit of claim 3, wherein the third and fourth transistors are NMOS transistors.

5. The sense amplifier circuit of claim 1, wherein the current mirror circuit comprises:

a third transistor having a first terminal for receiving the first current, a gate electrically connected to the first terminal, and a second terminal;

a fourth transistor having a gate electrically connected to the gate of the third transistor, a first terminal electrically connected to the gate of the first transistor, and a second terminal;

a fifth transistor having a first terminal electrically connected to the second terminal of the third transistor, a gate electrically connected to the first terminal, and a second terminal electrically connected to the low bias supply; and

a sixth transistor having a first terminal electrically connected to the second terminal of the fourth transistor, a gate electrically connected to the gate of the fifth transistor, and a second terminal electrically connected to the low bias supply.

6. The sense amplifier circuit of claim 5, wherein the third through sixth transistors are NMOS transistors.

7. The sense amplifier circuit of claim 1, further comprising:

a first non-volatile memory unit having a first terminal electrically connected to a high bias supply, and a second terminal electrically connected to the first terminal of the current mirror circuit for outputting the first current; and

a second non-volatile memory unit having a first terminal electrically connected to the high bias supply, and a second terminal electrically connected to the second terminal of the current mirror circuit for outputting a second current.

8. The sense amplifier circuit of claim 7, wherein each of the first and the second non-volatile memory units comprises:

a third transistor having a gate receiving a second control signal, a first terminal electrically connected to the high bias supply, and a second terminal; and

a non-volatile memory device having a first terminal electrically connected to the second terminal of the third transistor, wherein a second terminal of the non-volatile memory device of the first non-volatile memory unit is electrically connected to the first terminal of the current mirror circuit and a second terminal of the non-volatile memory device of the second non-volatile memory unit is electrically connected to the second terminal of the current mirror circuit.

9. The sense amplifier circuit of claim 8, wherein the third transistor is a PMOS transistor and the non-volatile memory device is a floating-gate (FG) PMOS embedded memory cell.

10. A sense amplifier circuit for a semiconductor memory device, comprising:

a latch circuit having a first terminal and a second terminal;

a first transistor having a first terminal electrically connected to a high bias supply, a second terminal electrically connected to the first terminal of the latch circuit, and a gate;

a second transistor having a first terminal electrically connected to the high bias supply, a second terminal electrically connected to the second terminal of the latch circuit, and a gate for receiving a first control signal; and

a current mirror circuit having a first terminal for receiving a first current, a second terminal electrically connected to the gate of the first transistor, a third terminal electrically connected to the high bias supply, and a fourth terminal electrically connected to the high bias supply wherein the latch circuit comprises;

a first inverter having an input terminal electrically connected to the second terminal of the first transistor, and an output terminal electrically connected to the second terminal of the second transistor; and

a second inverter having an input terminal electrically connected to the second terminal of the second transistor, and an output terminal electrically connected to the second terminal of the first transistor.

11. The sense amplifier circuit of claim 10, wherein the first and second transistors are PMOS transistors.

12. The sense amplifier circuit of claim 11, wherein the current mirror circuit comprises:

a third transistor having a first terminal electrically connected to the high bias supply, a second terminal for receiving the first current, and a gate electrically connected to the second terminal; and

a fourth transistor having a gate electrically connected to the gate of the third transistor, a first terminal electrically connected to the high bias supply, and a second terminal electrically connected to the gate of the first transistor.

13. The sense amplifier circuit of claim 12, wherein the third and fourth transistors are PMOS transistors.

14. The sense amplifier circuit of claim 10, wherein the current mirror circuit comprises:

a third transistor having a first terminal, a second terminal for receiving the first current, and a gate electrically connected to the second terminal;

a fourth transistor having a gate electrically connected to the gate of the third transistor, a first terminal, and a second terminal electrically connected to the gate of the first transistor;

a fifth transistor having a first terminal electrically connected to the high bias supply, a second terminal electrically connected to the first terminal of the third transistor, and a gate electrically connected to the second terminal; and

a sixth transistor having a first terminal electrically connected to the high bias supply, a gate electrically connected to the gate of the fifth transistor, and a second terminal electrically connected to the first terminal of the fourth transistor.

15. The sense amplifier circuit of claim 14, wherein the third through sixth transistors are PMOS transistors.

16. The sense amplifier circuit of claim 10, further comprising:

a first non-volatile memory unit having a first terminal electrically connected to the first terminal of the current mirror circuit for outputting the first current, and a second terminal electrically connected to a low bias supply; and

a second non-volatile memory unit having a first terminal electrically connected to the second terminal of the current mirror circuit for outputting a second current, and a second terminal electrically connected to the low bias supply.

17. The sense amplifier circuit of claim 16, wherein each of the first and the second non-volatile memory units comprises:

a third transistor having a gate for receiving a second control signal, a first terminal, and a second terminal electrically connected to the low bias supply; and

a non-volatile memory device having a first terminal electrically connected to first terminal of the third transistor, wherein a second terminal of the non-volatile memory device of the first non-volatile memory unit is electrically connected to the first terminal of the current mirror circuit and a second terminal of the non-volatile memory device of the second non-volatile memory unit is electrically connected to the second terminal of the current mirror circuit.

18. The sense amplifier circuit of claim 17, wherein the third transistor is an NMOS transistor and the non-volatile memory device is a floating-gate (FG) NMOS embedded memory cell.