Clock alignment detection from single reference

• US 7,664,213 B2
• Filed: 11/22/2005
• Issued: 02/16/2010
• Est. Priority Date: 11/22/2005
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Hassan, Mahmudul
• Primary Examiner(s): Ghayour; Mohammad H
• Assistant Examiner(s): Hassan; Sarah
• Application Number:
  US11/285,265
• Publication Number:
  US 20070116164A1
• Time in Patent Office: 1,547 Days
• Field of Search: 375/354, 327/291
• US Class Current: 375/354
• CPC Class Codes: H03K 5/125 Discriminating pulses measuring characteristics of individual pulses G01R29/02; separation of synchronising signals in television systems H04N5/08
• CPC Class Codes: H03K 5/26 the characteristic being duration, interval, position, frequency, or sequence
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A data communications system is disclosed. The data communications system comprises two clock domains. Each of the clock domains are coupled to receive a source clock signal. The first clock domain includes a first clock signal and the second clock domain includes a second clock signal, each of the first clock signal and the second clock signal are derived from the source clock signal. The first clock signal has a frequency which is different from that of the second clock signal, and which is not an integer multiple of the frequency of the second clock signal. The first clock domain includes circuitry which is configured to generate both the first clock signal and a reference clock signal derived from the source clock signal. The first clock domain is further configured to utilize the first clock signal to sample the reference clock signal, and assert an aligned signal responsive to detecting an edge of the reference clock signal, wherein the aligned signal indicates an edge of the first clock signal is aligned with an edge of the second clock signal.

Claims

1. A data communications system comprising:

a source clock signal;

a first clock domain comprising a first clock signal which is derived from the source clock signal, wherein the first clock signal has a first frequency; and

a second clock domain comprising a second clock signal which is derived from the source clock signal, wherein the second clock signal has a second frequency which is different from the first frequency, and wherein both the first frequency and the second frequency are an integer multiple of a frequency of the reference clock signal, and the first frequency is not an integer multiple of the second frequency;

wherein the first clock domain includes circuitry which is configured to;

generate a reference clock signal derived from the source clock signal;

generate the first clock signal;

utilize the first clock signal to sample the reference clock signal;

assert an aligned signal responsive to detecting an edge of the reference clock signal, wherein the aligned signal indicates an edge of the first clock signal is aligned with an edge of the second clock signal;

sample said reference clock signal on each falling edge of the first clock signal;

detect a sequence wherein said reference clock signal is low on a first cycle of the first clock signal, and said reference clock signal is high on a cycle of the first clock signal immediately following the first cycle; and

assert a pre-aligned signal which indicates a rising edge of the reference clock signal has been detected, responsive to detecting said sequence.

2. The system as recited in claim 1, wherein said circuitry is further configured to assert the aligned signal a predetermined number of cycles of the first clock signal subsequent to assertion of the pre-aligned signal.

3. The system as recited in claim 2, wherein the reference clock signal has a frequency which is half that of the source clock signal.

4. An apparatus comprising:

a clock circuit coupled to receive a source clock signal, wherein the clock circuit is configured to;

generate a first clock signal which is derived from the source clock signal, wherein the first clock signal has a first frequency; and

generate a reference clock signal derived from the source clock signal, wherein the reference clock signal has a frequency different than the first frequency;

an alignment detection unit coupled to receive the reference clock signal and the first clock signal, wherein the alignment detection unit is configured to;

utilize the first clock signal to sample the reference clock signal; and

generate a signal indicative of an alignment between an edge of the first clock signal and an edge of a second clock signal which is derived from the source clock signal, and wherein the second clock signal has a frequency different than the first frequency, and wherein both the first frequency and the second frequency are an integer multiple of a frequency of the reference clock signal, and the first frequency is not an integer multiple of the second frequency;

sample the reference clock signal on each falling edge of the first clock signal;

detect a sequence wherein said reference clock signal is low on a first cycle of the first clock signal, and said reference clock signal is high on a cycle of the first clock signal immediately following the first cycle; and

assert a pre-aligned signal which indicates a rising edge of the reference clock signal has been detected, responsive to detecting said sequence.

5. The apparatus as recited in claim 4, further comprising a counter unit configured to assert an aligned signal a predetermined number of cycles of the first clock signal subsequent to assertion of the pre-aligned signal.

6. The apparatus as recited in claim 5, wherein the reference clock signal has a frequency which is half that of the source clock signal.

7. A method for determining of alignment of clock signals comprising:

receiving a source clock signal in a first clock domain and a second clock domain;

generating a first clock signal from the source clock signal in the first clock domain, wherein the first clock signal has a first frequency; and

generating a reference clock signal from the source clock signal in the first clock domain;

generating a second clock signal in the second clock domain, wherein the second clock signal is derived from the source clock signal, and wherein the second clock signal has a second frequency which is different from the first frequency, wherein both the first frequency and the second frequency are an integer multiple of a frequency of the reference clock signal, and the first frequency is not an integer multiple of the second frequency;

utilizing the first clock signal to sample the reference clock signal; and

asserting an aligned signal responsive to detecting an edge of the reference clock signal, wherein the aligned signal indicates an edge of the first clock signal is aligned with an edge of the second clock signal;

sampling the reference clock signal on each falling edge of the first clock signal;

detecting a sequence wherein said reference clock signal is low on a first cycle of the first clock signal, and said reference clock signal is high on a cycle of the first clock signal immediately following the first cycle; and

asserting a pre-aligned signal which indicates a rising edge of the reference clock signal has been detected, responsive to detecting said sequence.

8. The method as recited in claim 7, further comprising asserting an aligned signal a predetermined number of cycles of the first clock signal subsequent to assertion of the pre-aligned signal.

9. The method as recited in claim 8, wherein the reference clock signal has a frequency which is half that of the source clock signal.