System and method for transferring data among transceivers substantially void of data dependent jitter
First Claim
1. A clock generation circuit, comprising:
- a detection circuit coupled to receive a stream of data having a repeating pattern of data regularly interspersed within a preamble portion of the stream of data, and to generate an edge during the preamble portion, and during a time no more than one bit after which the pattern of data ends, but not during prior transitions of the pattern of data;
an oscillator coupled to generate a plurality of regularly spaced clock pulses phase synchronized to the edge;
a window state machine coupled to receive a first clock generated from the stream of data and to produce a window pulse synchronized to the first clock and having a duration that begins prior to the edge and ends after the edge; and
logic coupled to produce the edge only during times when the window pulse exist.
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Accused Products
Abstract
A communication system, clock generation circuit, and method are provided for receiving jitter upon data and to generate a clock reference that does not contain the received jitter. The clock reference can be used either by a digital subsystem of a communication system node, or can be transmitted as substantially jitter-free data from that node to a downstream node of the communication system. Instead of recovering the clock reference from the data having jitter, a pattern is regularly defined within the data stream preferably at periodic, timed intervals. The data pattern may be made up of a series of non-transitions which, regardless of any jitter in the data itself, does not impute any jitter onto a phase-locked loop triggered from an edge of the non-transitioning data pattern. Using the edge as a reference point, a jitter-free clocking signal can be derived at the same frequency as a clocking signal which would normally be produced from the jitter-induced data.
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Citations
19 Claims
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1. A clock generation circuit, comprising:
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a detection circuit coupled to receive a stream of data having a repeating pattern of data regularly interspersed within a preamble portion of the stream of data, and to generate an edge during the preamble portion, and during a time no more than one bit after which the pattern of data ends, but not during prior transitions of the pattern of data; an oscillator coupled to generate a plurality of regularly spaced clock pulses phase synchronized to the edge; a window state machine coupled to receive a first clock generated from the stream of data and to produce a window pulse synchronized to the first clock and having a duration that begins prior to the edge and ends after the edge; and logic coupled to produce the edge only during times when the window pulse exist. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A communication system, comprising:
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a receiver coupled to receive a repeating pattern of bit values regularly interspersed within a preamble portion of a data stream and to generate an edge during the preamble portion, and no more than one bit after each said pattern terminates, wherein one of a plurality of regular clock pulses are generated in phase with the edge; a synchronous circuit coupled to process data synchronized to the plurality of regular clock pulses; a window state machine coupled to produce a window pulse synchronized to a first clock generated from the data stream, beginning before the edge and ending after the edge; and logic coupled to produce the edge only during times when the window pulse exists. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A method for transferring data substantially free of jitter, comprising:
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generating an edge during a preamble portion of a stream of data, and at the same time relative to an end of a consistent and unchanging pattern of bit values, but not during the pattern of bit values, and not more than one bit after the pattern of data ends; producing a window pulse synchronized to a first clock generated from the data stream, beginning before the edge and ending after the edge; producing the edge only during times when the window pulse exists; receiving the stream of data transitioning at a rate dependent on a logic value of the data; compiling a first clocking signal having jitter dependent on a frequency at which the rate changes; compiling a second clocking signal synchronized to the edge and having regularly occurring pulses transitioning at substantially the same rate as the first clocking signal; and transferring the data synchronized to the second clocking signal. - View Dependent Claims (18, 19)
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Specification