Method and system for efficient framing on addressed buses

• US 7,664,898 B2
• Filed: 02/01/2006
• Issued: 02/16/2010
• Est. Priority Date: 02/01/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Loyola, Guillermo A., Nuckolls, Neal, Siener, Stephen G., Jin, Changxi
• Primary Examiner(s): Cleary; Thomas J
• Application Number:
  US11/345,014
• Publication Number:
  US 20070180173A1
• Time in Patent Office: 1,476 Days
• Field of Search: 710/3, 710/4, 710/30, 710/105, 710/106, 710/301, 710/260, 714/799, 714/807, 709/216
• US Class Current: 710/106
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus

Abstract

A framing mechanism may be provided that enables passing of messages over an addressed bus. This creates a form of information hiding, which passes information by converting an addressed bus interface to a message-based bus interface. Address-based information in a transaction may be replaced with additional information that specifies framing details comprising, for example, a check pattern and length information. The check pattern provides a mechanism for determining whether frame information may be valid. An end device may utilize this length information to determine an actual length of an incoming frame. The combination of the check pattern and the length information may provide a pattern for resynchronizing a data stream when errors are detected. The framing mechanism may operate over existing addressed buses without requiring host side controller hardware modifications and additional host side software driver may be utilized to add the framing information.

Claims

1. A method for transmitting data from a first device to a second device over a bus, said method comprising:

configuring a portion of a frame to include a frame length and a frame length checksum of said frame, said configuring controlled by a code at said first device;

first transmitting an interrupt from said first device indicating that at least one frame is available for reading by said second device;

receiving a tag read command from said second device by said first device for reading said frame length and said frame length checksum;

second transmitting said frame length and said frame length checksum from said first device in response to said tag read command; and

third transmitting an amount of data indicated by said frame length from said first device to a second device via said bus using a bus protocol if said frame length is successfully validated by said frame length checksum.

2. The method according to claim 1, wherein said bus protocol is one of:

a PCMCIA/CF bus protocol and a SD bus protocol.

3. The method according to claim 1, wherein said frame length checksum comprises a bit-wise inverse of said frame length.

4. The method according to claim 1, further comprising processing said frame based on using at least one specific address.

5. The method of claim 1 wherein said configuring a portion of said frame further comprises appending a command block comprising a function number that determines whether said frame length and said frame length checksum is to be checked if said bus comprises an SDIO bus.

6. The method of claim 5 wherein said function number comprises 3 bits.

7. The method of claim 5 wherein said command block comprises CMD 53.

8. The method of claim 1 wherein said frame length is specified using two bytes.

9. The method of claim 1 wherein said frame length checksum is specified using two bytes.

10. The method of claim 1 further comprising fourth transmitting a specified four byte pattern in response to said tag read if said at least one frame is not available.

14. The machine-readable storage according to claim 9, wherein said at least one code section is used for processing said frame based on using at least one specific address.

11. A machine-readable storage having stored thereon, a computer program having at least one code section for transmitting information from a first device to a second device, the at least one code section being executable by a machine for causing the machine to perform steps comprising:

configuring a first portion of a frame with a frame length and a frame length checksum of said frame;

first transmitting said frame length and said frame length checksum to said second device via a bus using a bus protocol; and

second transmitting a second portion of said frame from said first device to said second device via said bus using said bus protocol if said length information is successfully validated using said checksum information by said second device.

12. The machine-readable storage according to claim 11, wherein said bus protocol is one of:

a PCMCIA/CF bus protocol and a SD bus protocol.

13. The machine-readable storage according to claim 11, wherein said frame length checksum comprises a bit-wise inverse of said frame length.

15. A first device comprising:

an interface to a bus; and

a CPU for addressing a second device through said interface, said second device storing a frame of a group of at least one frame, said CPU used for first reading a function number of a field in said frame of a group of at least one frame, said CPU used for determining if said function number equals a specified value, said CPU used for second reading a frame header comprising frame length and frame length checksum information if said function number is of a specified value, said CPU used for verifying whether said frame length is valid based on using said checksum information after said second reading occurs, wherein said first device receives an amount of data indicated by said frame length if said frame length is valid.

16. The first device of claim 15 wherein said function number comprises 3 bits.

17. The first device of claim 15 wherein said frame length information comprises 2 bytes.

18. The first device of claim 15 wherein said frame length checksum information comprises 2 bytes.

19. The first device of claim 15 wherein said bus employs a PCMCIA/CF protocol.

20. The first device of claim 15 wherein said bus employs a SDIO protocol.

21. The first device of claim 15 wherein said second device comprises an SD memory card used for storing said at least one frame.

22. A method of transmitting SDIO data frames over a bus comprising:

first reading a function number from a header of an SDIO data frame, said header comprising said function number, a frame length of said SDIO data frame, and a frame length checksum of said SDIO data frame;

second reading said frame length and said frame length checksum if said function number equals a specified value;

validating said frame length using said frame length checksum; and

processing an amount of data indicated by said frame length if said frame length is successfully validated.

23. The method of claim 22 wherein said function number comprises 3 bits.

24. The method of claim 22 wherein said frame length comprises 2 bytes.

25. The method of claim 22 wherein said frame length checksum comprises 2 bytes.

26. A system comprising:

one or more circuits operable for, at least;

first reading a function number from a header of an SDIO data frame, said header comprising said function number, a frame length of said SDIO data frame, and a frame length checksum of said SDIO data frame;

second reading said frame length said frame length checksum if said function number equals a specified value;

validating said frame length using said frame length checksum; and

processing an amount of data indicated by said frame length if said frame length is successfully validated.

27. The system of claim 26 wherein said function number comprises 3 bits.

28. The system of claim 26 wherein said frame length comprises 2 bytes.

29. The system of claim 26 wherein said frame length checksum comprises 2 bytes.