Semantic processor systems and methods

• US 7,664,938 B1
• Filed: 02/15/2007
• Issued: 02/16/2010
• Est. Priority Date: 01/07/2004
• Status: Expired due to Fees

• Current Assignee: Xambala Corporation
• Original Assignee: Xambala Corporation
• Inventors: Chandran, Sarin, Muthukrishnan, Raman, Tripathi, Devendra
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US11/675,618
• Time in Patent Office: 1,097 Days
• Field of Search: None
• US Class Current: 712/220
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A system including a CPU including logic for executing code from a location and at a time determined by an external entity, a data cache and a CPU management entity (CME) including logic for receiving data one unit at a time from an external data feeder. The data unit being arbitrarily defined mutually between the data feeder and the CME. The CME being coupled to the CPU. The CME including logic to provide the received data unit, a corresponding context information and a corresponding code address to the CPU, wherein the CPU includes logic for notifying the CME of a completed execution.

Claims

1. A system comprising:

a central processing unit (CPU) including logic for executing code from a storage location and at a time determined by an external entity;

a data cache; and

a CPU management entity (CME) including logic for receiving data one unit at a time from an external data feeder, the data unit being arbitrarily defined mutually between the data feeder and the CME, and the CME being coupled to the CPU, the CME including logic to provide the received data unit, a corresponding context information and a corresponding code address to the CPU, wherein the CPU includes logic for notifying the CME of a completed execution wherein the CME includes a plurality of command, control and condition registers, wherein each bit of a plurality of bits in the command register defines a trigger for a corresponding hardware or software function and wherein each bit of a plurality of bits in the command register is self clearing.

2. The system in claim 1, wherein the CPU is an embedded CPU.

3. The system in claim 2, wherein the CME is hardware logic.

4. The system in claim 1, wherein the CME includes a local buffer agent coupled to an external memory system, wherein the local buffer agent includes logic for allocating and de-allocating memory buffer pointers.

5. The system of claim 4, wherein the CME includes an enhanced memory access (EMA) coupled to the external memory system and wherein the system includes logic for saving and storing data structures as objects.

6. The system in claim 1, wherein the CME further includes a plurality of command, control and condition registers.

7. The system of claim 6, wherein each bit of a plurality of bits in the command register defines a trigger for a corresponding hardware or software function.

8. The system of claim 7, wherein each bit of a plurality of bits in the command register is self clearing.

9. The system of claim 6, wherein one or more bits of a plurality of bits in the control register define a mode of a software or a hardware function.

10. The system of claim 9, wherein at least one of the one or more bits of the plurality of bits in the control register are not self clearing.

11. The system of claim 6, wherein one or more bits of a plurality of bits in the condition register define a completion or an error status of a software or a hardware function.

12. The system of claim 6, wherein at least one of the plurality of command, control and condition registers, includes a flag to indicate to a thread controller to schedule another thread.

13. The system of claim 1, wherein the CPU includes a level 1 instruction cache and wherein the CME includes logic for determining if a starting instruction is available in the level 1 instruction cache before the CPU executes code associated with the received data.

14. The system of claim 13, wherein if the starting instruction is not available in the level 1 instruction cache, then including logic for pre-fetching the starting instruction from an external instruction memory into the level 1 instruction cache.

15. The system of claim 14, wherein, the size of the pre-fetch is configurable.

16. The system of claim 1, wherein the CPU includes a level 1 instruction cache and a level 2 instruction cache, the level 1 instruction cache being logically closer to the CPU and wherein the CME includes logic for determining if a starting instruction is available in the level 1 instruction cache and wherein if the starting instruction is not available in the level 1 instruction cache, then including logic for determining if the starting instruction is available in the level 2 instruction cache and if the starting instruction is available in the level 2 instruction cache then including logic for pre-fetching the starting instruction from the level 2 instruction cache into the level 1 instruction cache and if the starting instruction is not available in the level 2 instruction cache then including logic for pre-fetching the starting instruction from an external instruction memory into the level 1 instruction cache.

17. The system of claim 1, wherein the CME is coupled to a memory system for storing and retrieving context information.

18. A method of executing code in an embedded CPU comprising:

accessing executable code from a storage location and at a time determined by a central processing unit (CPU) management entity (CME), wherein the CME is external from the CPU and wherein the CPU includes a data cache;

determining a data unit size in the data feeder and in the CME, the CME being coupled to the CPU;

receiving data from the storage location, the data being received one unit at a time, wherein receiving the data unit includes providing a corresponding context information and a corresponding code address to the CPU;

executing the received data unit in the CPU; and

notifying the CME that the received data unit execution is completed wherein the CME includes a plurality of command, control and condition registers, wherein each bit of a plurality of bits in the command register defines a trigger for a corresponding hardware or software function and wherein each bit of a plurality of bits in the command register is self clearing.

19. The method of claim 18, wherein the CPU is an embedded CPU.

20. The method of claim 19, wherein the CME is hardware logic.

21. The method of claim 18, wherein the CME includes a local buffer agent coupled to an external memory system, wherein the method further includes allocating and de-allocating memory buffer pointers in the local buffer agent.

22. The method of claim 21, wherein the CME includes an enhanced memory access (EMA) coupled to the external memory system and wherein the method further includes saving and storing data structures as objects.

23. The method of claim 18, wherein one or more bits of a plurality of bits in the control register define a mode of a software or a hardware function.

24. The method of claim 23, wherein at least one of the one or more bits of the plurality of bits in the control register are not self clearing.

25. The method of claim 18, wherein one or more bits of a plurality of bits in the condition register define a completion or an error status of a software or a hardware function.

26. The method of claim 18, wherein at least one of the plurality of command, control and condition registers includes a flag to indicate to a thread controller to schedule another thread.

27. The method of claim 18, wherein the CPU includes a level 1 instruction cache and wherein the method further includes determining if a starting instruction is available in the level 1 instruction cache before the CPU executes code associated with the received data.

28. The method of claim 18, wherein the CPU includes a level 1 instruction cache and a level 2 instruction cache, the level 1 instruction cache being logically closer to the CPU and wherein the method further includes determining if a starting instruction is available in the level 1 instruction cache and wherein if the starting instruction is not available in the level 1 instruction cache, then determining if the starting instruction is available in the level 2 instruction cache and if the starting instruction is available in the level 2 instruction cache then pre-fetching the starting instruction from the level 2 instruction cache into the level 1 instruction cache and if the starting instruction is not available in the level 2 instruction cache then pre-fetching the starting instruction from an external instruction memory into the level 1 instruction cache.