Multi-core integrated circuit with shared debug port

• US 7,665,002 B1
• Filed: 12/14/2005
• Issued: 02/16/2010
• Est. Priority Date: 12/14/2005
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: White, Scott A., Wood, Timothy J., Clark, Michael T.
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US11/302,942
• Time in Patent Office: 1,525 Days
• Field of Search: 714/724, 714/726, 714/727, 714/729, 714/733, 714/734, 714/742
• US Class Current: 714/733
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/318583 Design for test
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

A single test access port, such as a JTAG-based debug port may be utilized to perform debug operations on logic cores of a multi-core integrated circuit, such as a multi-core processor. The shared debug port may respond to a particular command to enter a debugging mode and may be configured to forward all commands and data to a debugging controller of the integrated circuit during debugging. A mask register may be used to indicate which logic cores of the multi-core integrated circuit should be debugged. Additionally, custom debugging commands may include mask or core select fields to indicate which logic cores should be affected by the particular command. Debugging mode may be initialized for one or more logic cores either externally, such as be asserted a DBREQ signal, or internally, such as by configuring one or more breakpoints.

Claims

1. An integrated circuit, comprising:

a plurality of logic cores;

a debug controller coupled to each of the plurality of logic cores;

a test access port coupled to the debug controller and configured to provide an external interface to the debug controller; and

a core mask register configured to store a value indicating a selected one or more of the plurality of logic cores, wherein the core mask register is writable via the test access port;

wherein the debug controller is configured to switch the selected one or more logic cores from a normal mode of execution to a debug mode;

wherein, while in the normal execution mode, each of the logic cores is configured to execute program instructions;

wherein, while in the debug mode, each of the logic cores is configured to perform debug operations controlled by the debug controller according to commands received via the test access port; and

wherein each of the logic cores is capable of operating in the normal execution mode simultaneously with at least another one of the logic cores operating in the debug mode.

2. The integrated circuit of claim 1, wherein the debug controller comprises a plurality of core debug controllers each coupled to a respective one of the plurality of logic cores, wherein to perform the debug operations on one or more of the plurality of logic cores, the debug controller is configured to route commands received via the test access port to one or more of the respective core debug controllers based upon the value stored in the core mask register.

3. The integrated circuit of claim 1, wherein to perform said debug operations the debug controller is further configured to store a value to a register of each of the one or more of the plurality of logic cores indicated by the value stored in the core mask register based upon a single write command received via the test access port.

4. The integrated circuit of claim 1, wherein the test access port is a IEEE 1149.1-1990 compliant test access port.

5. The integrated circuit of claim 1, wherein the test access port is configured to disable the normal mode of operation and enter a pass-through mode in response to an input command, wherein while in the pass-through mode, the test access port is further configured to forward any received data or commands to the debug controller.

6. The integrated circuit of claim 1, wherein the debug controller is configured to request the one or more logic cores to enter the debug mode in response to the assertion of a DBREQ signal from test equipment external to the integrated circuit.

7. The integrated circuit of claim 1, wherein the debug controller is further configured to assert a DBRDY signal to test equipment external to the integrated circuit in response to the one or more logic cores entering the debug mode.

8. The integrated circuit of claim 1, wherein the debug controller is configured to execute one or more debug operations on at least one of the one or more of the plurality of logic cores based upon a command received via the test access port, wherein the received command indicates the at least one of the one or more of the plurality of logic cores.

9. The integrated circuit of claim 1, wherein each of the plurality of logic cores is configured to disable the normal mode of operation and enter the debug mode in response to encountering a breakpoint during processing, and wherein in response to one or more of the plurality of logic cores entering the debug mode, the debug controller is configured to assert a DBRDY signal to test equipment external to the integrated circuit to indicate that the one or more of the plurality of logic cores have entered the debug mode.

10. The integrated circuit of claim 9, wherein the debug controller is configured to assert the DBRDY signal only after every logic core indicated by the core mask register has entered the debug mode.

11. A method, comprising:

storing a value in a core mask register of a multi-core integrated circuit via a test access port of the integrated circuit, wherein the value indicates a selected one or more of a plurality of logic cores of the integrated circuit;

the multi-core integrated circuit receiving a debug request signal to request that the selected one or more of the plurality of logic cores of the integrated circuit switch from a normal mode of execution to a debug mode, wherein while in the debug mode, each selected logic core is configured to perform debug operations controlled by a debug controller of the integrated circuit according to debug commands received via the test access port;

in response to receiving one or more debug commands, the debug controller issuing one or more debug operations to each of the selected one or more of the plurality of logic cores; and

simultaneously with the selected one or more of the plurality of logic cores operating in the debug mode, the logic cores not selected to switch from the normal mode of execution to the debug mode remaining in normal execution mode and executing program instructions.

12. The method of claim 11, further comprising

the debug controller issuing the one or more debug operations to each of the selected one or more of the plurality of logic cores according to the value stored in the core mask register.

13. The method of claim 12, wherein the debug controller issues each of the one or more debug operations simultaneously to each of the one or more of the plurality of logic cores indicated by the value stored in the core mask register.

14. The method of claim 11, wherein the debug controller comprises a plurality of core debug controllers each coupled to a respective one of the plurality of logic cores, and wherein the debug controller is configured to issue each of the one or more debug commands to a corresponding one of the plurality of core debug controllers, wherein in response to receiving the one or more debug commands from the debug controller, each of the plurality of core debug controllers is configured to implement each of the one or more debug operations on the respective one of the plurality of logic cores.

15. The method of claim 11, wherein the test access port is a IEEE 1149.1-1990 compliant test access port.

16. The method of claim 11, further comprising the test access port disabling a normal mode of operation an entering a pass-through mode in response to an input command, wherein while in the pass-through mode, the test access port is configured to forward any input data or commands to the debug controller.

17. The method of claim 11, further comprising:

asserting a DBREQ signal from test equipment external to the integrated circuit; and

in response to said asserting, the debug controller requesting the one or more of the plurality of logic cores to enter the debug mode.

18. The method of claim 11, further comprising the debug controller asserting a DBRDY signal to test equipment external to the integrated circuit in response to the one or more of the plurality of logic cores entering the debug mode.

19. The method of claim 11, further comprising the debug controller executing one or more debug operations on at least one of the one or more of the plurality of logic cores based upon a debug command received via the test access port, wherein the received command indicates the at least one of the one or more of the plurality of logic cores.

20. A computer system, comprising:

a system memory; and

a multi-core microprocessor coupled to the system memory, comprising;

a plurality of processor cores;

a debug controller coupled to each of the plurality of processor cores;

a test access port coupled to the debug controller and configured to provide an external interface to the debug controller; and

a core mask register configured to store a value indicating a selected one or more of the plurality of logic cores, wherein the core mask register is writable via the test access port;

wherein the debug controller is configured to switch the selected one or more logic cores from a normal mode of execution to a debug mode;

wherein, while in the normal execution mode, each of the logic cores is configured to execute program instructions;

wherein, while in the debug mode, each of the logic cores is configured to perform debug operations controlled by the debug controller according to commands received via the test access port;

wherein each of the logic cores is capable of operating in the normal execution mode simultaneously with at least another one of the logic cores operating in the debug mode.