Retrial and reread methods and apparatus for recording channels

• US 7,665,007 B2
• Filed: 06/30/2004
• Issued: 02/16/2010
• Est. Priority Date: 06/30/2004
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Kurtas, Erozan, Yang, Xueshi
• Primary Examiner(s): Chaudry; M. Mujtaba K
• Assistant Examiner(s): Ahmed; Enam
• Application Number:
  US10/881,398
• Publication Number:
  US 20060002689A1
• Time in Patent Office: 2,057 Days
• Field of Search: 714/755, 714/55, 714/814
• US Class Current: 714/755
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/18 Error detection or correction; Testing , e.g. of drop-outs

Abstract

A method of reading a data block from a sector of a recording media is described. The data block from the sector of the recording channel is decoded with an ECC decoder (first trial). The data block is re-decoded (second trial) using an adjusted timing recovery block that is adjusted based on the decoded data block, if the number of errors exceeded an error correction capability of the ECC decoder on the first trial. In one embodiment, the data block is reread from the same sector of the recording channel using the adjusted timing recovery block that is adjusted based on the re-decoded data block. The data block is subsequently jointly decoded with the waveforms obtained from the second trial by a possibly modified sequence detector, if the number of errors exceeded the error correction capability of the ECC decoder during the second trial.

Claims

1. A method of reading a data block from a data channel, the method comprising:

reading a data block from the data channel;

decoding the data block with a decoding circuit to obtain a decoded data block during a first trial, wherein the decoding circuit utilizes a timing recovery algorithm to perform timing recovery on the data block to obtain the decoded data block; and

in response to the decoded data block exceeding an error correction capability of the decoding circuit, performing a re-decoding operation during a second trial using the decoded data block from the first trial, wherein performing the re-decoding operation comprises;

encoding at least a portion of the decoded data block from the first trial to obtain a re-encoded data block;

adjusting the timing recovery algorithm based on the re-encoded data block; and

re-decoding the data block using the adjusted timing recovery algorithm to obtain a re-decoded data block.

2. The method of claim 1 further comprising:

determining that the re-decoded data block exceeded an error correction capability of the decoding circuit and, in response, rereading the data block from the data channel using the adjusted timing recovery algorithm that is adjusted based on the re-decoded data block.

3. The method of claim 1 wherein the decoding circuit comprises:

timing recovery circuitry for synchronizing sampled waveforms;

data detection circuitry for detecting data within the sampled waveforms; and

error correction decoding circuitry for correcting errors in the detected data.

4. The method of claim 1 wherein the data channel is a storage medium.

5. The method of claim 4 wherein decoding the data block comprises:

sampling waveforms on the storage medium to read the data block;

synchronizing the sampled waveforms according to the timing recovery algorithm;

detecting the data block in a detector; and

decoding the detected data block with an ECC decoder.

6. The method of claim 5 wherein the detector comprises a sequence detector.

7. The method of claim 6 wherein the sequence detector is selected from a group consisting of a Viterbi detector, a soft-output Viterbi Algorithm and a BCJR algorithm.

8. The method of claim 1 wherein reading the data block comprises sampling a waveform from the data channel, and wherein the step of decoding comprises decoding the sampled waveform into a decoded bit sequence, the method further comprising:

storing the sampled waveform in a buffer.

9. The method of claim 8, wherein encoding comprises re-encoding the decoded bit sequence from the decoding circuit with an ECC encoder, and wherein the adjusting step comprises performing timing recovery using the re-encoded bit sequence and the stored waveform to obtain re-synchronized signal samples, and wherein the re-decoding step comprises detecting the data block using the re-synchronized signal samples with a sequence detector and decoding the detected data block using the decoding circuit without rereading the data block from the data channel.

10. The method of claim 9 wherein performing timing recovery comprises:

re-sampling the stored waveform using a decision-directed timing recovery scheme.

11. The method of claim 10 wherein the decision-directed timing recovery scheme comprises a Mueller and Mü

ller synchronization algorithm or a minimum mean square error timing recovery algorithm.

12. The method of claim 10 wherein the decision-directed timing recovery scheme is operated under decisions from the re-encoded data sequence from the ECC encoder.

13. The method of claim 2 wherein the data channel is a storage medium, and wherein encoding comprises encoding the decoded data block with an ECC encoder, and wherein rereading comprises:

rereading the data block from a sector of the storage medium;

synchronizing the reread signal using a decision directed timing recovery algorithm where the decisions are a re-encoded bit sequence from the encoding step;

detecting the synchronized signal samples with a detector; and

decoding the detected data block with an ECC decoder.

14. The method of claim 13 wherein the detector produces an output to the decoder based on the reread signal samples, the signal samples from a first read operation, and correctly decoded codewords from the first read operation.

15. A method of decoding a data block after a data block failure in a first trial, the method comprising:

sampling readback waveforms representative of a data block from a data channel;

synchronizing the sampled readback waveforms according to a timing recovery algorithm;

detecting an encoded first bit sequence within the synchronized readback waveforms using a detector;

decoding the detected first bit sequence with an ECC decoder during a first trial; and

in response to the decoded first bit sequence exceeding an error correction capability of the ECC decoder, performing a decoding operation during a second trial using the decoded first bit sequence from the first trial, wherein performing the decoding operation during the second trial comprises;

re-encoding at least a portion of the data bits from the first bit sequence that were decoded during the first trial;

re-synchronizing the sampled readback waveforms representative of the data block using a decision-directed timing recovery algorithm directed with the re-encoded data bits from the first trial;

detecting a second bit sequence within the re-synchronized waveforms using the detector; and

decoding the detected second bit sequence with the ECC decoder in a second trial.

16. The method of claim 15 and further comprising:

storing the readback waveforms in a buffer; and

storing the resynchronized waveform samples in the buffer.

17. The method of claim 16 wherein the step of re-synchronizing comprises:

calculating estimates of ideal partial response equalized samples d_k using the re-encoded data bits; and

updating a sampling phase with the calculated estimates and the stored readback waveforms.

18. The method of claim 15 wherein if decoding the detected second bit sequence produces a number of symbol errors which exceeds an error correction capability of the ECC decoder, the method comprises:

performing a reread operation.

19. The method of claim 18 wherein performing a reread operation comprises:

reading another copy of the readback waveform representative of the same data block from the channel;

synchronizing the reread waveform with a decision-directed timing recovery algorithm using decisions from the re-encoded data bits from the first trial;

detecting a bit sequence within the synchronized reread waveform with a detector which performs joint detection on the synchronized reread waveform and a stored synchronized waveform from the first trial, under the direction of previously correctly decoded codewords;

decoding the detected bit sequence using an ECC decoder; and

sending the decoded bit sequence to a user if the ECC decoding step is successful;

wherein the method is repeated if a number of symbol errors exceeds an error correction capability of the ECC decoder.

20. A decoder for decoding data from a data channel, the decoder comprising:

a data channel input for receiving signals from the data channel; and

a decoder circuit coupled to the data channel input and configured to perform a first decoding operation on a portion of data received from the data channel input using a timing recovery algorithm to decode the portion of data; and

wherein the decoder circuit selectively performs a second decoding operation using decoded data from the first decoding operation if a number of errors of a data block in the first decoding operation exceeds an error correction capability of the decoder circuit, wherein the decoder circuit performs the second decoding operation by adjusting the timing recovery algorithm using re-encoded data from the first decoding operation and performing the second decoding operation on the portion of data using the adjusted timing recovery algorithm without rereading data from the data channel, wherein the decoder circuit selects a number of correctly decoded codewords from the first decoding operation and uses the adjusted timing recovery algorithm and the correctly decoded codewords to perform the second decoding operation.

21. The decoder of claim 20 wherein the decoder is configured to reread the data channel if the second decoding operation fails.

22. The decoder of claim 20 wherein the reread data is decoded by the decoder circuit.

23. The decoder of claim 20 wherein the decoder circuit comprises:

a timing recovery circuit coupled to the data channel input and configured to synchronize signals from the data channel input.

24. The decoder of claim 20 and further comprising:

an error correction code decoder configured to decode data and to correct errors contained within the data; and

a failure detection circuit configured to detect when a number of errors contained within the data exceeds an error correction capability of the error correction code decoder.

25. The system of claim 24 and further comprising:

a timing recovery circuit responsive to decisions from a previously decoded and re-encoded data sequence.

26. The decoder of claim 20 wherein the decoder is configured to reread the data, the decoder further comprising:

a data sequence detector configured to perform joint detection of two copies of synchronized waveform samples from the same data block.

27. The system of claim 20 wherein the data channel comprises:

a storage medium or any other communication channel wherein data transmission is block based.