Methods of forming wiring to transistor and related transistor
First Claim
1. A method of forming wiring to a transistor, the method comprising:
- forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate;
forming a dielectric layer over the transistor;
bonding the dielectric layer to another substrate;
removing the silicon substrate from the SOI substrate to the buried insulator layer;
forming a contact to each of the source/drain region and the gate from a channel side of the gate; and
forming at least one wiring to the contacts on the channel side of the gate.
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Accused Products
Abstract
Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate.
219 Citations
17 Claims
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1. A method of forming wiring to a transistor, the method comprising:
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forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method of forming wiring to a transistor, the method comprising:
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forming a transistor on a semiconductor layer positioned over an etch stop layer positioned over a silicon substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each; forming an insulating layer over the transistor; bonding the dielectric to another substrate, the another substrate including one of;
a blank substrate and a substrate including at least one of the following;
devices and wiring patterned therein;removing the silicon substrate to the etch stop layer; forming a contact through the etch stop layer to each of the source/drain region and the gate, wherein the contact forming includes; patterning and etching a contact via hole through the etch stop layer to each of the source/drain region and the gate, etching through the source/drain region to expose a conductor thereof and through or to the gate to expose a conductor thereof, wherein the conductor includes;
a) for the source/drain region, a silicide of the source/drain region, and b) for the gate;
b1) in the case that the gate includes polysilicon, a silicide of the gate, or b2) in the case that the gate includes a metal, the metal of the gate, andforming metal in the contact via holes; and forming at least one wiring to the contacts.
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Specification