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Methods of forming wiring to transistor and related transistor

  • US 7,666,723 B2
  • Filed: 02/22/2007
  • Issued: 02/23/2010
  • Est. Priority Date: 02/22/2007
  • Status: Expired due to Fees
First Claim
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1. A method of forming wiring to a transistor, the method comprising:

  • forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate;

    forming a dielectric layer over the transistor;

    bonding the dielectric layer to another substrate;

    removing the silicon substrate from the SOI substrate to the buried insulator layer;

    forming a contact to each of the source/drain region and the gate from a channel side of the gate; and

    forming at least one wiring to the contacts on the channel side of the gate.

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