Non-volatile semiconductor device and method of fabricating embedded non-volatile semiconductor memory device with sidewall gate

• US 7,667,259 B2
• Filed: 06/14/2006
• Issued: 02/23/2010
• Est. Priority Date: 06/20/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kimura, Shin-Ichiro, Hisamoto, Digh, Yasui, Kan, Ishimaru, Tetsuya
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US11/452,256
• Publication Number:
  US 20070145455A1
• Time in Patent Office: 1,350 Days
• Field of Search: 257/314, 257/324, 257/326
• US Class Current: 257/314
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

Claims

1. A non-volatile semiconductor device comprising:

a plurality of split gate type memory cells in a first area above a semiconductor substrate; and

a logic circuit in a second area above the semiconductor substrate,

wherein said split gate type memory cells have a plurality of select gate electrode structures and a plurality of memory gate electrode structures,

wherein said select gate electrode structures comprise a select gate dielectric film and at least one kind of a select gate electrode material in the first area;

wherein said memory gate electrode structures comprise a memory gate dielectric film and a memory gate electrode material formed as a plurality of side wall structures relative to the select gate electrode structures,

wherein said logic circuit has a plurality of logic circuit gate electrode structures which comprise the select gate dielectric material and the select gate electrode material in the second area which includes said logic circuit and which is not overlapping the first area, and

wherein a height of said logic circuit gate electrode structures is lower than a height of said memory gate electrode structures.

2. The non-volatile semiconductor device according to claim 1,

wherein said split gate type memory cells and said logic circuit each include diffusion regions formed by self-alignment method of an ion implantation on a side of channels of transistors included in said split gate type memory cells and said logic circuit.

3. The non-volatile semiconductor device according to claim 1,

wherein said select gate electrode material and said memory gate electrode material each include an amorphous silicon layer.