Shallow source MOSFET

• US 7,667,264 B2
• Filed: 09/27/2004
• Issued: 02/23/2010
• Est. Priority Date: 09/27/2004
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Ho, Moses, Tai, Sung-Shan, Li, Tiesheng, Chang, Hong
• Primary Examiner(s): Warren; Matthew E
• Application Number:
  US10/952,231
• Publication Number:
  US 20060071268A1
• Time in Patent Office: 1,975 Days
• Field of Search: 257329-331, 257/E29.256, 257/E29.257, 257/E29.26
• US Class Current: 257/330
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device comprises a drain, a body in contact with the drain, the body having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a trench extending through the source and the body to the drain, and a gate disposed in the trench, having a gate top surface that extends substantially above the body top surface. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.

Claims

1. A semiconductor device comprising:

a drain;

a body in contact with the drain, the body having a body top surface;

a plurality of source regions embedded in the body, extending downward from the body top surface into the body;

a trench extending through the plurality of source regions and the body to the drain, said trench having a trench opening and a trench wall; and

a gate disposed in the trench, said gate having a gate top surface that extends substantially above the body top surface at least in the center region of the trench opening, and said gate having a vertical edge that includes an extended portion extending above the trench opening, the extended portion being substantially aligned with the trench wall; and

a plurality of spacers insulating the source from the gate, each of the plurality of spacers being situated immediately adjacent to the gate and immediately adjacent to a respective one of the plurality of source regions, wherein each of the plurality of spacers does not substantially extend into the trench and does not substantially extend over the trench;

a dielectric layer disposed over the source, the spacers, the gate, and at least a portion of the body, the dielectric layer forming a contact opening that has a width that is narrower than a distance between edges of the source regions; and

a metal layer disposed over the dielectric layer, making a contact with the body at the contact opening.

2. A semiconductor device as recited in claim 1, wherein the gate is insulated by a dielectric layer.

3. A semiconductor device as recited in claim 1, wherein the gate has a side that is substantially perpendicular with respect to the body top surface.

4. A semiconductor device as recited in claim 1, wherein the trench is formed using a SiO₂ hard mask.

5. A semiconductor device as recited in claim 1, wherein the trench has a wall formed by having been mutually aligned with the gate.

6. A semiconductor device as recited in claim 1, wherein the trench is mutually aligned with the gate.

7. A semiconductor device as recited in claim 1, wherein the source is no more than 0.5 μ

m deep.

8. A semiconductor device as recited in claim 1, wherein the gate extends above the body top surface by at least 300 Å

.

9. A semiconductor device as recited in claim 1, further comprising a silicide layer connecting the source to the metal layer.

10. A semiconductor device as recited in claim 1, wherein the gate fills the trench opening and extends substantially above the body top surface in approximately all of the trench opening.

11. A semiconductor device as recited in claim 1, wherein the spacer is made of dielectric material.

12. A semiconductor device as recited in claim 9, wherein the gate includes a silicide top layer.

13. A semiconductor device as recited in claim 11, wherein the silicide top layer of the gate is disconnected from the silicide layer connecting the source to the metal contact.