Varying mesa dimensions in high cell density trench MOSFET

• US 7,667,265 B2
• Filed: 07/07/2006
• Issued: 02/23/2010
• Est. Priority Date: 01/30/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Sim, Gordon George, Wang, Qi
• Primary Examiner(s): Gurley; Lynne A.
• Assistant Examiner(s): Webb; Vernon P
• Application Number:
  US11/482,676
• Publication Number:
  US 20070176231A1
• Time in Patent Office: 1,327 Days
• Field of Search: 257/213, 257/288, 257327-330, 257/368, 257/401, 438/149, 438/197
• US Class Current: 257/330
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/66325 controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Circuits, methods, and apparatus for power MOSFETs having a high cell density for a high current carrying capability while maintaining a low pinched-base resistance. One device employs a number of transistor cells having varying mesa (regions between trench gates) sizes. A heavy body etch is utilized in larger cells to reduce the pinched-base resistance. This etch removes silicon in the mesa region, which is then replaced with lower-impedance aluminum. A number of smaller cells that do not receive this etch are used to increase device current capacity. Avalanche current is directed to the larger, lower pinched base cells by ensuring these cells have a lower BVDSS breakdown voltage. The large cell BVDSS can be varied by adjusting the critical dimension or width of the trench gates on either side of the wider mesas, or by adjusting the depth of the heavy body etch.

Claims

1. A field effect transistor comprising:

a first plurality of cells having a first cell pitch, the first plurality of cells having gates with first mesa regions extending between the gates, wherein a heavy body contact opening extends into each first mesa region, and a heavy body region extends in each first mesa regions along a bottom of corresponding heavy body contact opening; and

a second plurality of cells having a second cell pitch, the second cell pitch being narrower than the first cell pitch, the second plurality of cells having gates with second mesa regions extending between the gates, wherein no heavy body contact opening is formed in the second mesa regions, and a heavy body region extends in each second mesa region to a shallower depth than a depth to which the heavy body regions in the first mesa regions extend;

wherein each of the gates in the first and second plurality of cells is housed in a trench, each mesa region in the first and second plurality of cells including a well region, the well regions in at least the second plurality of cells including source regions having a conductivity type opposite that of the well regions;

wherein each of the heavy body regions in the first and the second mesa regions is located in a corresponding well region, the heavy body regions being of the same conductivity type as but having a higher doping concentration than the well regions.

2. The transistor of claim 1 wherein the heavy body region in each first mesa regions is used to control a body-diode breakdown voltage for the first plurality of cells.

3. The transistor of claim 1 wherein a width of a trench is used to control a body-diode breakdown voltage for the first plurality of cells.

4. The transistor of claim 1 wherein a desired turn off current specification is used to determine a number of cells in the first plurality of cells.

5. The transistor of claim 4 wherein a desired on resistance is used to determine a number of cells in the second plurality of cells.

6. The transistor of claim 1 wherein the second pitch is determined by minimum design rules.

7. The transistor of claim 1 wherein at least one of the trenches extending adjacent one of the mesa regions in the first plurality of cells is shallower than at least one of the trenches extending adjacent one of the mesa regions in the second plurality of cells.

8. The transistor of claim 1 further comprising a top electrode contacting the source regions and the heavy body regions in the second plurality of cells, the top electrode further extending into the heavy body contact openings to contact the heavy body regions in the first plurality of cells.

9. A trench-gate power field effect transistor comprising:

a first trench gate;

a second trench gate displaced from the first trench gate by a first distance in a first direction, the region between the first and second trench gates being free from trench gates;

a third trench gate displaced from the second trench gate by a second distance in a second direction opposite the first direction, the region between the second and third trench gates being free from trench gates;

a first well region located between the first trench gate and the second trench gate, the first well region having a heavy body contact opening extending therein;

a first heavy body region extending in the first well region along a bottom of the heavy body contact opening;

a second well region located between the second trench gate and the third trench gate, the second well region having no heavy body contact opening extending therein; and

a second heavy body region extending in the second well region to a shallower depth than a depth to which the first heavy body region extends,

wherein the first distance is larger than the second distance.

10. The transistor of claim 9 wherein only the first well region receives a heavy body etch so that a heavy body contact opening is formed in the first well region but not in the second well region.

11. The transistor of claim 9 wherein the first trench gate is shallower than the third trench gate.

12. The transistor of claim 9 wherein at least the second well region includes source regions having a conductivity type opposite that of the first and second well regions, and each of the first, second and third trench gates includes a gate therein.

13. The transistor of claim 12 wherein the first and second heavy body regions are of the same conductivity type as but have a higher doping concentration than the first and second well regions.

14. The transistor of claim 13 further comprising a top electrode contacting the source regions and the second heavy body region, the top electrode further extending into the heavy body contact opening to contact the first heavy body region.

15. A field effect transistor comprising:

a first pair of gates with a first well region extending between the first pair of gates, and with no gates between the first pair of gates;

a second pair of gates with a second well region extending between the second pair of gates, and with no gates between the second pair of gates, wherein of the first and second well regions, only the first well region has a heavy body contact opening extending therein, and the first well region has a lateral width greater than a lateral width of the second well region;

a first heavy body region extending in the first well region along a bottom of the heavy body contact opening; and

a second heavy body region extending in the second well region to a shallower depth than a depth to which the first heavy body region extends.

16. The transistor of claim 15 further comprising:

a first pair of trenches each housing one of the first pair of gates, a spacing between the first pair of trenches defining the lateral width of the first well region; and

a second pair of trenches each housing one of the second pair of gates, a spacing between the second pair of trenches defining the lateral width of the second well region.

17. The transistor of claim 16 wherein the first pair of trenches extend to a shallower depth than do the second pair of trenches.

18. The transistor of claim 15 wherein at least the second well region includes source regions therein, the source regions having a conductivity type opposite that of the first and second well regions.

19. The transistor of claim 18

wherein the first and second heavy body regions are of the same conductivity type as but have a higher doping concentration than the first and second well regions.

20. The transistor of claim 19 further comprising a top electrode contacting the source regions and the second heavy body region, the top electrode further extending into the heavy body contact opening to contact the first heavy body region.