Trench gate type semiconductor device

• US 7,667,269 B2
• Filed: 04/06/2006
• Issued: 02/23/2010
• Est. Priority Date: 04/28/2005
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Tokura, Norihito, Yamamoto, Kensaku, Ozeki, Yoshihiko, Tsuzuki, Yukio
• Primary Examiner(s): Parker; Kenneth A
• Assistant Examiner(s): Diaz; Jose R
• Application Number:
  US11/398,551
• Publication Number:
  US 20060244053A1
• Time in Patent Office: 1,419 Days
• Field of Search: 257/341
• US Class Current: 257/341
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; a fourth semiconductor layer in a part of the third semiconductor layer; a trench penetrating the fourth semiconductor layer and the third semiconductor layer and reaching the second semiconductor layer; a gate insulation film on an inner wall of the trench; a gate electrode on the gate insulation film in the trench; a first electrode; and a second electrode. The trench includes a bottom with a curved surface having a curvature radius equal to or smaller than 0.5 μm.

Claims

1. A trench gate type semiconductor device comprising:

a first semiconductor layer having a first conductive type or a second conductive type;

a second semiconductor layer having the second conductive type and disposed on a surface of the first semiconductor layer;

a third semiconductor layer having the first conductive type and disposed on a surface of the second semiconductor layer;

a fourth semiconductor layer having the second conductive type and disposed in a part of a surface portion of the third semiconductor layer;

a trench penetrating from the surface of the third semiconductor layer through the fourth semiconductor layer and the third semiconductor layer and reaching the second semiconductor layer;

a gate insulation film disposed on an inner wall of the trench;

a gate electrode disposed on the gate insulation film in the trench;

a first electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer; and

a second electrode electrically connected to the first semiconductor layer, wherein

the trench includes a bottom having a curved surface,

the curved surface of the bottom of the trench has a curvature radius equal to or smaller than 0.5 μ

m,

the gate insulation film includes a bottom part and a side part,

the bottom part of the gate insulation film is disposed on the bottom of the trench,

the side part of the gate insulation film is disposed on a sidewall of the trench,

the bottom part of the gate insulation film has a thickness, which is thicker than a thickness of the side part of the gate insulation film,

the third semiconductor layer includes a first portion and a second portion, which are electrically separated by the trench,

the first portion of the third semiconductor layer is electrically connected to the first electrode, and

the second portion of the third semiconductor layer is electrically disconnected to the first electrode.

2. The device according to claim 1, wherein

the thickness of the bottom part of the gate insulation film is equal to or more than twice thicker than that of the side part of the gate insulation film.

3. The device according to claim 2, wherein

the trench is perpendicular to the surface of the third semiconductor layer.

4. The device according to claim 2, wherein

the trench is slanted off the surface of the third semiconductor layer so that the trench has a tapered shape.

5. The device according to claim 1, wherein

the first semiconductor layer has the first conductive type,

the device provides an insulated gate bipolar transistor having a cell skipping structure, and

the second portion of the third semiconductor layer provides the cell skipping structure.

6. The device according to claim 1, wherein

the first semiconductor layer has the second conductive type, and

the device provides a metal oxide semiconductor field effect transistor.

7. The device according to claim 6, wherein

the metal oxide semiconductor field effect transistor has a cell skipping structure, and

the second portion of the third semiconductor layer provides the cell skipping structure.