Fin field-effect transistors

• US 7,667,271 B2
• Filed: 04/27/2007
• Issued: 02/23/2010
• Est. Priority Date: 04/27/2007
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Hsu, Yu-Rung, Yeh, Chen-Nan
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Patton; Paul E
• Application Number:
  US11/741,602
• Publication Number:
  US 20080265321A1
• Time in Patent Office: 1,033 Days
• Field of Search: 257/347, 257/401, 438/300, 438/481
• US Class Current: 257/347
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A fin field-effect transistor (finFET) with improved source/drain regions is provided. In an embodiment, the source/drain regions of the fin are removed while spacers adjacent to the fin remain. An angled implant is used to implant the source/drain regions near a gate electrode, thereby allowing for a more uniform lightly doped drain. The fin may be re-formed by either epitaxial growth or a metallization process. In another embodiment, the spacers adjacent the fin in the source/drain regions are removed and the fin is silicided along the sides and the top of the fin. In yet another embodiment, the fin and the spacers are removed in the source/drain regions. The fins are then re-formed via an epitaxial growth process or a metallization process. Combinations of these embodiments may also be used.

Claims

1. A fin field-effect transistor (finFET) comprising:

a substrate;

a fin having a first region, a second region, and a third region, the second region being interposed between the first region and the third region, the first region and the third region comprising a first material and the second region comprising a second material, the first material being different than the second material, the fin in the first region and the third region being completely formed of metal;

a gate dielectric overlying the substrate and the fin, the gate dielectric overlying the fin in the second region; and

a gate electrode overlying the gate dielectric.

2. The finFET of claim 1, wherein the substrate comprises a silicon substrate and further comprises a dielectric layer thereon, the silicon substrate extending through the dielectric layer under the fin.

3. The finFET of claim 1, further comprising fin spacers alongside the fin.

4. The finFET of claim 1, wherein the second material comprises a portion of a bulk silicon substrate.

5. The finFET of claim 1, further comprising a lightly-doped drain in the fin on opposing sides of the gate electrode.

6. The finFET of claim 5, wherein the lightly-doped drain extends substantially an entire height of the fin adjacent the gate electrode.

7. A fin field-effect transistor (finFET) comprising:

a substrate;

a dielectric layer formed over the substrate;

a fin extending from the substrate through the dielectric layer, the fin including source/drain regions and a channel region;

a gate dielectric overlying the substrate and the fin, the gate dielectric overlying a portion of the fin;

a gate electrode overlying the gate dielectric; and

gate spacers formed adjacent the gate electrode such that fin spacers adjacent to the fin are absent.

8. The finFET of claim 7, wherein the fin comprises a silicon substrate extending through the dielectric layer, a top surface and side surfaces of the fin being silicided.

9. The finFET of claim 7, wherein the source/drain regions comprise epitaxially grown material.

10. The finFET of claim 9, wherein the epitaxially grown material comprises epitaxially grown silicon, epitaxially grown silicon germanium, or epitaxially grown silicon carbon.

11. The finFET of claim 7, wherein a first dimension of the source/drain regions of the fin along a first axis normal to a longitudinal axis of the fin and parallel to a major surface of the substrate is greater than a second dimension of the channel region of the fin along a second axis parallel to the first axis.

12. The finFET of claim 7, wherein the source/drain regions comprise a metal.

13. A fin field-effect transistor (finFET) comprising:

a substrate;

a first dielectric layer overlying the substrate, a portion of the substrate extending through at least a portion of the first dielectric layer;

a gate dielectric overlying the first dielectric layer and a portion of the substrate extending through the gate dielectric;

a gate electrode overlying the gate dielectric;

spacers alongside opposing sides of the gate electrode; and

source/drain structures alongside the gate electrode, the source/drain structures comprising at least a first portion contacting the substrate extending through the first dielectric layer and at least a second portion overlying a portion of the first dielectric layer.

14. The finFET of claim 13, wherein the source/drain structures comprise epitaxially grown material.

15. The finFET of claim 14, wherein the epitaxially grown material comprises epitaxially grown silicon, epitaxially grown silicon germanium, or epitaxially grown silicon carbon.

16. The finFET of claim 13, wherein the source/drain structures comprise a metal.

17. The finFET of claim 13, wherein the source/drain structures comprise a silicide region.

18. The finFET of claim 13, wherein the substrate is a bulk silicon substrate.