Efficient pulse amplitude modulation transmit modulation

• US 7,667,511 B2
• Filed: 08/02/2005
• Issued: 02/23/2010
• Est. Priority Date: 05/23/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Maggio, Kenneth J., Leipold, Dirk, Staszewski, Robert B.
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): Hiltunen; Thomas J
• Application Number:
  US11/195,060
• Publication Number:
  US 20050264333A1
• Time in Patent Office: 1,666 Days
• Field of Search: 327172-176, 327/34, 331/14, 331/17, 331/25, 332/115, 332/117, 332/144, 332/149
• US Class Current: 327/172
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/2176 Class E amplifiers
• CPC Class Codes: H03K 5/06 by the use of delay lines or other analogue delay elements
• CPC Class Codes: H03K 7/02 Amplitude modulation, i.e. PAM
• CPC Class Codes: H04B 1/0483 Transmitters with multiple parallel paths
• CPC Class Codes: H04B 2001/0491 with frequency synthesizers, frequency converters or modulators

Abstract

Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.

Claims

1. A pulse amplitude modulator, comprising:

a power amplifier having an input port for receiving an oscillator clock signal and a plurality of digitally controlled parallel connected transistors that provide for amplitude modulation, wherein the plurality of digitally controlled parallel connected transistors comprises a first transistor coupled in parallel with a second transistor;

a matching network, the matching network coupled to said digitally controlled parallel connected transistors;

a digitally controlled oscillator (DCO) having an input;

a tuning word adjustment circuit coupled to the input, the tuning word adjustment circuit being responsive to an amplitude control signal; and

wherein said DCO is operable to provide the oscillator clock signal; and

a means for amplitude control of an output of the DCO in response to the amplitude control signal.

2. A pulse amplitude modulator as defined in claim 1, further comprising AND gates.

3. A pulse amplitude modulator as defined in claim 1, wherein the amplitude modulation is responsive to a selected number of said active parallel connected transistors.

4. A pulse modulator as defined in claim 1, further comprising means for controlling the number of said parallel connected transistors that are active in accordance with the digital control signal.

5. The pulse amplitude modulator as defined in claim 1, wherein the amplifier further comprises AND functionality.

6. The pulse amplitude modulator of claim 1, wherein an output amplitude of the power amplifier is generated via AND functionality.

7. A pulse amplitude modulator, comprising:

a power amplifier having an input port for receiving an input signal and a plurality of digitally controlled parallel connected transistors that provide for amplitude modulation, wherein the plurality of digitally controlled parallel connected transistors comprises a first transistor coupled in parallel with a second transistor;

a matching network, the matching network coupled to said digitally controlled parallel connected transistors;

a digitally controlled oscillator (DCO) having a second input; and

a tuning word adjustment circuit coupled to the second input, the tuning word adjustment circuit being responsive to an amplitude control signal; and

wherein said DCO is operable to provide the input signal for the power amplifier.

8. The pulse amplitude modulator as defined in claim 7, wherein the amplifier further comprises AND functionality.

9. The pulse amplitude modulator as defined in claim 7, wherein the digitally controlled parallel connected transistors provide for amplitude modulation of the input signal.

10. A transmitter circuit, comprising:

a pulse amplitude modulator (PAM) including;

a digitally controlled oscillator (DCO) having an input and further comprising a tuning word adjustment circuit coupled to the input of the DCO, the tuning word adjustment circuit being responsive to an amplitude control signal, the DCO providing a clock signal; and

a digitally controlled power amplifier receiving and responsive to the DCO clock signal and the amplitude control signal.

11. A transmitter circuit as defined in claim 10, wherein the tuning word adjustment circuit changes the DCO frequency for a single clock cycle, whereby the amplitude control signal and a phase control signal input to the tuning word adjustment circuit are orthogonal.

12. A transmitter circuit as defined in claim 10, wherein the amplitude control signal performs amplitude modulation.

13. The transmitter circuit as defined in claim 10, wherein the amplitude control signal is generated via AND functionality.