Voltage switch circuit of semiconductor device

• US 7,667,521 B2
• Filed: 05/16/2008
• Issued: 02/23/2010
• Est. Priority Date: 05/16/2007
• Status: Active Grant

• Current Assignee: DB HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Lee, Yong Seop
• Primary Examiner(s): Nguyen; Long
• Assistant Examiner(s): Goyal; Shikha
• Application Number:
  US12/122,373
• Publication Number:
  US 20080284492A1
• Time in Patent Office: 648 Days
• Field of Search: 327/108, 327/109, 327/112, 327/390, 327/333, 327/423, 327/424, 327/427, 327/536, 326/80, 326/81, 326/83, 326/88, 365/189.11
• US Class Current: 327/333
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors

Abstract

Disclosed is a voltage switch circuit of a semiconductor device. The subject voltage switch circuit can be used to apply voltage to a semiconductor memory device control circuit. The voltage switch circuit according to an embodiment includes five transistors and a capacitor. An output terminal of the subject circuit outputs VSS when VDD is applied to an input terminal, and outputs a boosted operating voltage when VSS is applied to the input terminal.

Claims

1. A voltage switch circuit of a semiconductor device, the voltage switch circuit comprising:

a first transistor and a second transistor coupled to a third terminal, wherein the third terminal receives an enable signal;

a third transistor and a fourth transistor coupled to a second terminal, wherein the second terminal receives an operating voltage,

wherein the first transistor is connected in series with the third transistor through a second node and the second transistor is connected in series with the fourth transistor through a first node, wherein the third transistor connects to the first node and the fourth transistor connects to the second node to provide a coupling circuit;

a fifth transistor connected in series between the first node and a fourth terminal, wherein the fourth terminal provides an output voltage; and

a capacitor connected at a first end to a first terminal and at a second end to the fourth terminal in parallel with the fifth transistor, wherein the first terminal receives a clock signal;

wherein the fourth terminal outputs a VSS voltage when a VDD voltage is input to the third terminal, and outputs a boosted operating voltage when the VSS voltage is input to the third terminal.

2. The voltage switch circuit according to claim 1, wherein the first transistor is coupled to the third terminal through a first conduction terminal of the first transistor, and wherein the second transistor is coupled to the third terminal couples through a control terminal of the second transistor.

3. The voltage switch circuit according to claim 2, wherein VDD is applied to a control terminal of the first transistor, and wherein VSS is applied to a first conduction terminal of the second transistor.

4. The voltage switch circuit according to claim 3, wherein the first transistor and the second transistor comprise NMOS transistors, wherein the first conduction terminal of the first transistor is the source of the first transistor and the control terminal of the first transistor is the gate of the first transistor, and wherein the first conduction terminal of the second transistor is the source of the second transistor and the control terminal of the second transistor is the gate of the second transistor.

5. The voltage switch circuit according to claim 1, wherein the third transistor is coupled to the second terminal at a first conduction terminal of the third transistor, and wherein the first transistor is connected in series with the third transistor using a second conduction terminal of the third transistor and a second conduction terminal of the first transistor.

6. The voltage switch circuit according to claim 1, wherein the fourth transistor is coupled to the second terminal at a first conduction terminal of the fourth transistor, and wherein the second transistor is connected in series with the fourth transistor using a second conduction terminal of the fourth transistor and a second conduction terminal of the second transistor.

7. The voltage switch circuit according to claim 1, wherein a control terminal of the third transistor is connected to the first node, and a control terminal of the fourth transistor is connected to the second node to provide the coupling circuit.

8. The voltage switch circuit according to claim 7, wherein the third transistor and the fourth transistor comprise PMOS transistors, wherein the control terminal of the third transistor is the gate of the third transistor and the control terminal of the fourth transistor is the gate of the fourth transistor.

9. The voltage switch circuit according to claim 1, wherein the fifth transistor comprises:

a first conduction terminal connected to the first node,

a second conduction terminal connected to the fourth terminal, and

a control terminal for receiving an applied VDD voltage.

10. The voltage switch circuit according to claim 9, wherein the fifth transistor comprises an NMOS transistor.

11. The voltage switch circuit according to claim 1, wherein the fourth terminal provides the output voltage to a semiconductor device control circuit, and wherein the operating voltage received by the second terminal comprises an operating voltage for the semiconductor device control circuit.

12. The voltage switch circuit according to claim 11, wherein the boosted operating voltage is greater than a numerical value obtained by adding the operating voltage of the semiconductor device control circuit to threshold voltage of a transistor of the semiconductor device control circuit.

13. The voltage switch circuit according to claim 12, wherein the semiconductor device control circuit controls writing, reading and erasing operations of a memory device.

14. The voltage switch circuit according to claim 1, wherein the first, second and fifth transistors are NMOS transistors, and the third and fourth transistors are PMOS transistors.

15. The voltage switch circuit according to claim 1, wherein the capacitor continuously receives alternating VDD and VSS from the clock signal input through the first terminal, such that the capacitor boosts voltage at the fourth terminal.