LVDS receiver for controlling current based on frequency and method of operating the LVDS receiver

• US 7,667,546 B2
• Filed: 06/30/2005
• Issued: 02/23/2010
• Est. Priority Date: 07/02/2004
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dae-Gyu
• Primary Examiner(s): Tan; Vibol
• Assistant Examiner(s): Tabler; Matthew C
• Application Number:
  US11/173,485
• Publication Number:
  US 20060002483A1
• Time in Patent Office: 1,699 Days
• Field of Search: 326/82, 331 16- 17
• US Class Current: 331/16
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

In an embodiment, an LVDS (Low Voltage Differential Signaling) receiver includes at least one LVDS input buffer, a clock generating unit, and a bias circuit. The clock generating unit includes a voltage controlled oscillator for generating a clock signal tracking a frequency of data received via the at least one LVDS input buffer based on a control voltage. The bias circuit controls current sources that supply current to at least one differential amplifier in the at least one LVDS input buffer based on the control voltage of the clock signal generating unit. Therefore, the LVDS receiver can save current consumed in LVDS input buffers by controlling the amount of current supplied to the at least one differential amplifier included in the at least one LVDS input buffers.

Claims

1. A receiver comprising:

a plurality of data input buffers, each data input buffer configured to receive corresponding data transmitted from a transmitter, where the data is parallel data serialized into serial data;

a clock input buffer configured to receive a clock input signal transmitted from the transmitter;

a clock generating unit configured to generate a clock signal in response to the clock input signal, the clock generating unit including a voltage controlled oscillator configured to generate the clock signal that tracks a frequency of the data received by the input buffers based on a control voltage applied to the voltage controlled oscillator;

a bias circuit configured to control current sources for supplying current to the data input buffers based on the control voltage; and

a deserializer configured to convert the data received by each of the data input buffers into the corresponding parallel data in response to the clock signal.

2. The receiver according to claim 1, wherein the data input buffers have a rail-to-rail architecture.

3. The receiver according to claim 1, wherein the clock generating unit includes a phase locked loop (PLL).

4. The receiver according to claim 1, wherein the clock generating unit includes a delay locked loop (DLL).

5. The receiver according to claim 1, wherein the bias circuit controls the current sources so that the current sources supply the current substantially proportional to a square of the control voltage.

6. The receiver according to claim 1, wherein the bias circuit controls the current sources so that the current sources supply the current substantially linearly proportional to the control voltage.

7. The receiver according to claim 1, wherein the receiver is a low voltage differential signaling (LVDS) receiver and the data input buffers are LVDS buffers.

21. The receiver according to claim 1, wherein

the clock input buffer is configured to receive the clock input signal independent of the control voltage.

22. The receiver according to claim 1, wherein:

the clock generating unit further comprises a voltage-to-current converting circuit configured to generate a control current in response to the control voltage; and

the bias circuit is configured to provide the current sources with bias voltage corresponding to the control current.

23. The receiver according to claim 22, wherein the voltage-to-current converting circuit comprises:

an input transistor having a gate to which the control voltage is applied; and

a current mirror coupled to a drain of the input transistor to generate the control current substantially proportional to a square of the control voltage.

24. The receiver according to claim 22, wherein the voltage-to-current converting circuit comprises:

an input transistor having a gate to which the control voltage is applied;

a diode connected transistor coupled in parallel with the input transistor; and

a current mirror commonly coupled to a drain of the input transistor and a drain of the diode connected transistor to generate the control current substantially linearly proportional to the control voltage.

25. The receiver according to claim 21, wherein:

each data input buffer includes a corresponding current source of the current sources; and

the bias circuit is configured to control the current source of each input buffer in response to the control voltage.

8. A receiver comprising:

a plurality of data input buffers, each data input buffer configured to receive corresponding data transmitted from a transmitter, where the data is parallel data serialized into serial data;

a clock input buffer configured to receive a clock input signal transmitted from the transmitter;

a clock generating unit configured to generate a clock signal in response to the clock input signal;

a control voltage generating unit configured to generate a control voltage corresponding to a frequency of the data received by the data input buffers;

a bias circuit configured to generate at least one bias voltage for controlling at least one current source that supplies current to the data input buffers in response to the control voltage; and

a deserializer configured to convert the data received by each of the data input buffers into the corresponding parallel data in response to the clock signal.

9. The receiver according to claim 8, wherein the receiver is a low voltage differential signaling (LVDS) receiver and the data input buffers are LVDS buffers.

10. The receiver according to claim 8, wherein each data input buffer comprises:

a differential amplifier to receive a corresponding input signal; and

a corresponding current source of the at least one current source, the corresponding current source to supply current to the differential amplifier in response to the control voltage independent of the corresponding input signal.

11. The receiver according to claim 8, further comprising a register configurable by external commands, wherein the control voltage generating unit is configured to generate the control voltage in response to a value stored in the register.

12. The receiver according to claim 8, wherein the bias circuit controls the at least one current source so that the current source supplies the current either substantially proportional to a square of the control voltage or substantially linearly proportional to the control voltage.

13. A method of operating a receiver comprising:

receiving data transmitted from a transmitter to the receiver in a plurality of data input buffers, where the data associated with each data input buffer is parallel data serialized into serial data;

receiving a clock input signal transmitted from the transmitter to the receiver in a clock input buffer;

generating a clock signal that tracks a frequency of the data received via the data input buffers in response to the clock input signal;

generating a control voltage corresponding to the frequency of the data;

controlling current supplied to differential amplifiers of the data input buffers based on the control voltage;

operating the differential amplifiers based on the controlled current; and

converting the data received via each of the data input buffers into the corresponding parallel data in response to the clock signal.

14. The receiver according to claim 13, wherein the receiver is a low voltage differential signaling (LVDS) receiver and the data input buffers are LVDS buffers.

15. The method of claim 13, wherein the clock signal is generated by a phase locked loop (PLL).

16. The method of claim 15, wherein the control voltage corresponds to a control voltage of a voltage controlled oscillator of the PLL.

17. The method of claim 13, wherein the clock signal is generated by a delay locked loop (DLL).

18. The method of claim 17, wherein the control voltage corresponds to a control voltage of a voltage controlled oscillator of the DLL.

19. The method of claim 13, wherein the controlling current comprises supplying the current proportional to a square of the control voltage to the differential amplifiers of the data input buffers.

20. The method of claim 13, wherein the controlling current comprises supplying the current substantially linearly proportional to the control voltage to the differential amplifiers of the data input buffers.