Built-in self test for a CMOS imager

• US 7,667,751 B2
• Filed: 10/08/2003
• Issued: 02/23/2010
• Est. Priority Date: 05/29/2001
• Status: Active Grant

• Current Assignee: Transchip Israel Limited
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Antsiferov, Ilia, Galambos, Tiberiu C., Elmakias, Yair, Shnayder, Alexander, Furman, Ben, Fraenkel, Miriam
• Primary Examiner(s): Tran; Nhan T
• Assistant Examiner(s): Chon; Peter
• Application Number:
  US10/474,799
• Publication Number:
  US 20050128325A1
• Time in Patent Office: 2,330 Days
• Field of Search: 348/266, 348/272, 348/281, 348/282, 348/283, 348/288, 348/294, 348/298, 348/300, 348/301, 348/302, 348/303, 348/304, 348/306, 348/307, 348/308, 348/309, 348/310, 348/311, 348/319
• US Class Current: 348/294
• CPC Class Codes: H04N 11/20 Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 17/002 for television cameras
• CPC Class Codes: H04N 23/70 Circuitry for compensating brightness variation in the scene
• CPC Class Codes: H04N 23/71 Circuitry for evaluating the brightness variation
• CPC Class Codes: H04N 23/73 by influencing the exposure time
• CPC Class Codes: H04N 23/745 Detection of flicker frequency or suppression of flicker wherein the flicker is caused by illumination, e.g. due to fluorescent tube illumination or pulsed LED illumination
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 5/16 Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level
• CPC Class Codes: H04N 9/69 for modifying the colour signals by gamma correction controlling camera response for colour signals H04N23/83
• CPC Class Codes: H04N 9/73 Colour balance circuits, e.g. white balance circuits or colour temperature control camera processing pipelines for colour balance H04N23/88

Abstract

Systems, methods and devices related to detection and transmitting images. Imaging systems and devices, as well as methods of using such that are provided herein include flicker detection and/or correction; and/or built-in self test associated with various analog circuitry in the imaging devices; and/or power reduction ability; and/or pixels with charge evacuation functionality; and/or a parallel to serial conversion unit and associated serial output interface; and/or other advanced functionality.

Claims

1. A CMOS imaging device, the CMOS imaging device comprising:

a pixel array;

a selector, wherein the selector is operable to select between an input derived from the pixel array and at least one reference input, wherein the selection between the input derived from the pixel array and the at least one reference input is at least in part based on a signal derived from a digital domain, the input derived from the pixel array and the at least one reference input both being input to the selector, an output of the selector is passed through an analog processing circuit, the analog processing circuit including at least,

a level shift circuit coupled to a black offset circuit, the black offset circuit also being coupled to a programmable offset circuit, the programmable offset circuit also being coupled to a first stage programmable gain amplifier, the first stage programmable gain amplifier also being coupled to a second stage programmable gain amplifier;

an analog processing selector, wherein the analog processing selector is operable to bypass one or more portions of the analog processing circuit, the analog processing selector configured to output a first signal to bypass the level shift circuit, a second signal to bypass the black offset circuit, a third signal to bypass the first stage programmable gain amplifier, and a fourth signal to bypass the second stage programmable gain amplifier; and

an analog to digital converter, wherein the analog to digital converter is operable to convert a signal derived from the selector to the digital domain.

2. The CMOS imaging device of claim 1, the CMOS imaging device further comprising:

a comparator receiving an output from the analog to digital converter, wherein the comparator is selected from a group consisting of;

a programmable hardware comparator, a programmable software comparator, and a hardwired comparator.

3. The CMOS imaging device of claim 1, wherein the pixel array includes at least one pseudo-pixel, the CMOS imaging device further comprising:

a pixel array selector, wherein the pixel array selector is operable to select the at least one pseudo-pixel, and wherein the input derived from the pixel array is derived from the pseudo-pixel.

4. The CMOS imaging device of claim 3, the CMOS imaging device further comprising:

a column amplifier, wherein the column amplifier receives an output from the pseudo-pixel, and amplifies the output from the pseudo-pixel; and

wherein the input derived from the pixel array is derived via the column amplifier.

5. The CMOS imaging device of claim 1, wherein the reference input to the selector is a pixel under reset, the CMOS imaging device further comprising:

a circuit for selecting the pixel under reset; and

wherein the selector is operable to provide a differential pair consisting of the input derived from the pixel array and the pixel under reset.

6. The CMOS imaging device of claim 1, wherein at least one of the reference inputs to the selector is tied to a pad of the CMOS imaging device.

7. The CMOS imaging device of claim 1, wherein at least one of the reference inputs to the selector comprises one or more voltages generated internal to the CMOS imaging device.

8. The CMOS imaging device of claim 1, wherein the input derived from the pixel array and the at least one reference input are both differential inputs.

9. A method for testing analog functionality of a CMOS imaging device in the digital domain, the method comprising:

providing a pixel array;

providing a selector, wherein the selector is operable to select between an input derived from the pixel array and at least one reference input, the input derived from the pixel array and the at least one reference input both being input to the selector;

providing an analog to digital converter, wherein the analog to digital converter is operable to convert a signal derived from the selector to the digital domain;

asserting a selection signal in the digital domain, wherein a derivative of the selection signal is input to the selector and at least in part controls the selection between the input derived from the pixel array and the reference input;

analyzing an output of the analog to digital converter to verify that the CMOS imaging device is functional, wherein

the input derived from the pixel array is a differential input, the at least one reference input comprises a reset level, and the selection between the input derived from the pixel array and the reference input includes selecting one of the differential signals associated with the input derived from the pixel array and the reset level, and providing the input derived from the pixel array and the reset level as a differential pair;

resetting at least one pixel in the pixel array; and

selecting the at least one reset pixel, wherein the input derived from the pixel array is derived from the at least one reset pixel.

10. The method of claim 9, wherein the reference input is a differential input, and wherein the reference input is a combination of two signals selected from a group consisting of:

a common voltage, a negative reference voltage, and a positive reference voltage.

11. The method of claim 10, wherein asserting the selection signal causes the reference input to be selected, the method further comprising:

providing an analog processing circuit, wherein the analog processing circuit receives the reference input from the selector, and processes the reference input, and wherein the signal derived from the selector is the processed reference input.

12. The method of claim 11, wherein the analog processing circuit comprises a first circuit and a second circuit, the method further comprising:

bypassing the first circuit,

13. The method of claim 9, wherein the analyzing the output of the analog to digital converter comprises comparing the output of the analog to digital converter to determine if the output is within a predefined range.

14. The method of claim 9, wherein the pixel array includes at least one pseudo-pixel, the method further comprising:

selecting the pseudo-pixel, wherein an output of the pseudo pixel is not sensitive to an illumination of the CMOS imaging device, and wherein the input derived from the pixel array is derived from the output of the pseudo-pixel; and

wherein asserting the selection signal causes the input from the pixel array to be selected.

15. The method of claim 14, the method further comprising:

providing a column amplifier, wherein the input derived from the pixel array is derived via the column amplifier.

16. The method of claim 9, wherein the reference input is a differential input, and wherein at least one differential signal of the reference input is generated external to the CMOS imaging device.