Digitally controlled oscillator and associated method

• US 7,667,948 B1
• Filed: 02/11/2008
• Issued: 02/23/2010
• Est. Priority Date: 01/24/2005
• Status: Active Grant

• Current Assignee: Marvell Israel Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell Israel Limited (Marvell Technology Group Limited)
• Inventors: Moshe, David, Asa, Gil, Bourstein, Ido
• Primary Examiner(s): Ha; Nguyen T
• Application Number:
  US12/069,568
• Time in Patent Office: 743 Days
• Field of Search: 361/301.2, 361277-278, 361/280, 361290-292, 341/150, 341144-145
• US Class Current: 361/301.2
• CPC Class Codes: H03K 2005/00039 having four transistors serially
• CPC Class Codes: H03K 2005/00071 by adding capacitance as a load
• CPC Class Codes: H03K 2005/00123 Avoiding variations of delay due to integration tolerances
• CPC Class Codes: H03K 2005/00143 Avoiding variations of delay due to temperature
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

A digitally controlled capacitor includes a first set of N capacitors, wherein the first set has a first capacitance value and each of the M capacitors has a second capacitance value, and at least one second set of N capacitors. The second set has the first capacitance value and each of the N capacitors has a third capacitance value that is greater than the second capacitance value. M and N are integers greater than one and M is not equal to N.

Claims

1. A digitally controlled capacitor comprising:

a first set of M capacitors, wherein the first set has a first capacitance value and each of the M capacitors has a second capacitance value; and

at least one second set of N capacitors, wherein the second set has the first capacitance value and each of the N capacitors has a third capacitance value that is greater than the second capacitance value,

wherein M and N are integers greater than one and M is not equal to N.

2. The digitally controlled capacitor of claim 1 wherein the second capacitance value is approximately one half of the third capacitance value and N is one half of M.

3. The digitally controlled capacitor of claim 1 further comprising a third set of P capacitors, wherein the third set has the first capacitance value and each of the P capacitors has a fourth capacitance value that is greater than the third capacitance value.

4. The digitally controlled capacitor of claim 3 wherein the third capacitance value is approximately one half of the fourth capacitance value and P is one half of N.

5. The digitally controlled capacitor of claim 1 further comprising:

a first set of M switches that are each associated with a respective one of the M capacitors; and

a second set of N switches that are each associated with a respective one of the N capacitors.

6. The digitally controlled capacitor of claim 5 wherein each of the M and N switches includes a transistor and further comprising:

a level shifter that shifts gate levels of each of the transistors.

7. The digitally controlled capacitor of claim 1 further comprising:

a first shift register associated with the first set that provides a first control signal to the first set; and

at least one second shift register associated with the at least one second set that provides a second control signal to the second set.

8. The digitally controlled capacitor of claim 7 wherein the first and second shift registers store logical values that selectively determine states of the M capacitors and the N capacitors, respectively.