Dynamic random access memory circuit, design structure and method
First Claim
1. A memory circuit comprising:
- a memory cell comprising;
a memory cell capacitor electrically connected to ground and a memory cell transistor,wherein said memory cell capacitor exhibits a first capacitance, andwherein said memory cell transistor is adapted to electrically connect said memory cell capacitor to a first bit line when a first word line is active;
a reference cell comprising;
two reference cell capacitors connected in series and electrically connected to a reference plate and a reference cell transistor,wherein said two reference cell capacitors connected in series exhibit a second capacitance that is approximately one half said first capacitance,wherein said reference cell transistor is adapted to electrically connect said two reference cell capacitors connected in series to a second bit line when a second word line is active, andwherein said reference plate is adapted to apply a first voltage to said reference cell capacitors, when said first word line and said second word line are inactive, and further to apply a second voltage level different from said first voltage level to said two reference cell capacitors, when said first word line is active;
a precharge circuit adapted to precharge said first bit line and said second bit line to said first voltage level, when said first word line and said second word line are inactive; and
a sense amplifier adapted to detect a potential difference between said first bit line and said second bit line, during a read operation, when said first word line and said second word line are active.
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Accused Products
Abstract
Disclosed is a DRAM circuit that incorporates an improved reference cell, has half the capacitance of the memory cell, does not require a particular reference voltage, and can be formed using the same fabrication processes as the memory cell. This DRAM circuit comprises a memory cell with a single trench capacitor and a reference cell having two trench capacitors. The two reference cell trench capacitors are connected in series through a merged buried capacitor plate such that they provide half the capacitance of the memory cell trench capacitor. Additionally, the reference cell trench capacitors have essentially the same structure as the memory cell trench capacitor so that they can be formed in conjunction with the memory cell trench capacitor. Also disclosed are a design structure for the above-described memory circuit and a method for forming the above-described memory circuit.
9 Citations
20 Claims
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1. A memory circuit comprising:
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a memory cell comprising;
a memory cell capacitor electrically connected to ground and a memory cell transistor,wherein said memory cell capacitor exhibits a first capacitance, and wherein said memory cell transistor is adapted to electrically connect said memory cell capacitor to a first bit line when a first word line is active; a reference cell comprising;
two reference cell capacitors connected in series and electrically connected to a reference plate and a reference cell transistor,wherein said two reference cell capacitors connected in series exhibit a second capacitance that is approximately one half said first capacitance, wherein said reference cell transistor is adapted to electrically connect said two reference cell capacitors connected in series to a second bit line when a second word line is active, and wherein said reference plate is adapted to apply a first voltage to said reference cell capacitors, when said first word line and said second word line are inactive, and further to apply a second voltage level different from said first voltage level to said two reference cell capacitors, when said first word line is active; a precharge circuit adapted to precharge said first bit line and said second bit line to said first voltage level, when said first word line and said second word line are inactive; and a sense amplifier adapted to detect a potential difference between said first bit line and said second bit line, during a read operation, when said first word line and said second word line are active. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming a memory cell and reference cell for incorporation into a memory circuit, said method comprising:
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providing a wafer; and forming on said wafer a memory cell capacitor for said memory cell and two reference cell capacitors connected in series for said reference cell such that said memory cell capacitor and said two reference cell capacitors comprise substantially identical capacitor structures and such that said memory cell capacitor exhibits a first capacitance and said two reference cell capacitors connected in series exhibit a second capacitance that is approximately one half said first capacitance. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A design structure embodied in a machine readable medium, said design structure comprising a memory circuit comprising:
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a memory cell comprising;
a memory cell capacitor electrically connected to ground and a memory cell transistor,wherein said memory cell capacitor exhibits a first capacitance, and wherein said memory cell transistor is adapted to electrically connect said memory cell capacitor to a first bit line, when a first word line is active; a reference cell comprising;
two reference cell capacitors connected in series and electrically connected to a reference plate and a reference cell transistor,wherein said two reference cell capacitors connected in series exhibit a second capacitance that is approximately one half said first capacitance, wherein said reference cell transistor is adapted to electrically connect said two reference cell capacitors connected in series to a second bit line, when a second word line is active, and wherein said reference plate is adapted to apply a first voltage to said reference cell capacitors, when said first word line and said second word line are inactive, and further to apply a second voltage level different from said first voltage level to said two reference cell capacitors, when said first word line is active; a precharge circuit adapted to precharge said first bit line and said second bit line to said first voltage level, when said first word line and said second word line are inactive; and a sense amplifier adapted to detect a potential difference between said first bit line and said second bit line, during a read operation, when said first word line and said second word line are active. - View Dependent Claims (19, 20)
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Specification