Method of erasing non-volatile memory cells

• US 7,668,017 B2
• Filed: 08/17/2005
• Issued: 02/23/2010
• Est. Priority Date: 08/17/2005
• Status: Active Grant

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Lusky, Eli, Eitan, Boaz
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US11/205,716
• Publication Number:
  US 20070041249A1
• Time in Patent Office: 1,651 Days
• Field of Search: 365/185.29, 365/230.06, 365/185.14, 365/185.22
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

A method includes determining groups of rows to erase together in order to minimize the margin loss associated with bake after a large number of program and erasure cycles. The method alternatively includes determining groups of rows to erase together to minimize the width of a resultant erase threshold voltage distribution, erasing the groups together, stopping erasure of a group when the group is erase verified and performing the step of erasing on those groups which were not previously erase verified.

Claims

1. A non-volatile memory chip comprising:

a memory array of non-volatile memory cells formed into rows and columns;

a logic circuit adapted to determine groups of rows to erase together;

an X decoder to activate a row of said memory array; and

an erase flag register to identify groups of said rows to erase together.

2. The chip according to claim 1 and wherein each said group is a set of M consecutive rows.

3. The chip according to claim 1 and wherein each said group is a set of N rows aligned with a non-uniformity in said array.

4. The chip according to claim 1 and wherein each said group is a set of A rows aligned with a non-uniformity in programming speed of the array cells during program operation.

5. The chip according to claim 1 and wherein each said group is a set of B rows aligned with a non-uniformity in erase speed of the array cells during erase operation.

6. The chip according to claim 1 and wherein each said group is a set of C rows aligned with a non-uniformity in the distance of a row from a strapping location for said row.

7. The chip according to claim 1 and wherein each said group is a set of D rows which erased within the same number of pulses during a previous erase operation.

8. A method comprising:

determining groups of rows to erase together to minimize the width of a resultant erase threshold voltage distribution;

erasing said groups together;

stopping erasure of a group when said group is erase verified; and

performing said step of erasing on those groups which were not previously erase verified.

9. The method according to claim 8 and wherein each said group is a set of M consecutive rows.

10. The method according to claim 8 and wherein each said group is a set of N rows aligned with the array non-uniformity.

11. The method according to claim 8 and wherein each said group is a set of A rows aligned with a non-uniformity in programming level and speed of the array cells during program operation.

12. The method according to claim 8 and wherein each said group is a set of B rows aligned with a non-uniformity in erase speed of the array cells during erase operation.

13. The method according to claim 8 and wherein each said group is a set of C rows defined by the distance of a row from a strapping location for said row.

14. The method according to claim 8 and wherein each said group is a set of D rows which erased within the same number of pulses during a previous erase operation.

15. A method comprising:

determining groups of rows to erase together in order to minimize the margin loss associated with bake resulting from multiple program and erasure cycles.

16. The method according to claim 15 and wherein each said group is a set of M consecutive rows.

17. The method according to claim 15 and wherein each said group is a set of N rows aligned with the array non-uniformity.

18. The method according to claim 15 and wherein each said group is a set of A rows aligned with a non-uniformity in programming level and speed of the array cells during program operation.

19. The method according to claim 15 and wherein each said group is a set of B rows aligned with a non-uniformity in erase speed of the array cells during erase operation.

20. The method according to claim 15 and wherein each said group is a set of C rows defined by the distance of a row from a strapping location for said row.

21. The method according to claim 15 and wherein each said group is a set of D rows which erased within the same number of pulses during a previous erase operation.