Method for data converter sample clock distribution

• US 7,668,153 B2
• Filed: 07/06/2007
• Issued: 02/23/2010
• Est. Priority Date: 03/27/2007
• Status: Active Grant

• Current Assignee: CommScope Technologies, LLC (CommScope Holding Company, Inc.)
• Original Assignee: ADC Telecommunications Incorporated (TE Connectivity Limited)
• Inventors: Zavadsky, Dean
• Primary Examiner(s): Pham; Chi H.
• Assistant Examiner(s): HOM, SHICK C
• Application Number:
  US11/774,441
• Publication Number:
  US 20080240164A1
• Time in Patent Office: 963 Days
• Field of Search: None
• US Class Current: 370/350
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation

Abstract

A unit for use in a communication system comprises a communication module having an oscillator configured to generate a master clock signal; a plurality of conversion modules; and a distribution component configured to distribute the master clock signal from the communication module to each of the plurality of conversion modules. Each of the plurality of conversion modules comprises a filter configured to filter the master clock signal; and a converter configured to use the filtered master clock signal in converting between analog and digital signals.

Claims

1. A communication system comprising:

a host unit comprising;

a first module having a first oscillator configured to generate a first master clock signal having an amplitude-to-noise floor ratio that is insufficient to achieve a desired jitter level; and

a plurality of second modules coupled to the first module to receive the first master clock signal, each of the plurality of second modules having a first filter to filter the first master clock signal such that the amplitude-to-noise floor ratio is increased sufficiently to achieve the desired jitter level, and a first converter configured to use the filtered first master clock signal rather than a clock signal generated in the respective second module in converting between analog and digital signals;

a transport mechanism; and

at least one remote unit distributed in a coverage area, the at least one remote unit communicatively coupled to the host unit via the transport mechanism, wherein the at least one remote unit comprises;

a third module having a second oscillator configured to generate a second master clock signal having an amplitude-to-noise floor ratio that is insufficient to achieve the desired jitter level; and

a plurality of fourth modules coupled to the third module to receive the second master clock signal, each of the plurality of fourth modules having a second filter to filter the second master clock signal such that the amplitude-to-noise floor ratio is increased sufficiently to achieve the desired jitter level, and a second converter configured to use the filtered second master clock signal rather than a clock signal generated in the respective fourth module in converting between analog and digital signals.

2. The communication system of claim 1, wherein the transport mechanism comprises one of a fiber optic cable, a wireless millimeter wave signal transceiver, and a microwave radio transceiver.

3. The communication system of claim 1, wherein the first and third modules are configured to convert between serial data streams and digital radio frequency (RF) signals.

4. The communication system of claim 3, further comprising an optical multiplex module coupled to the first module and configured to multiplex optical serial data streams transported to the first module.

5. The communication system of claim 1, further comprising a base station coupled to at least one of the plurality of second modules, wherein the at least one second module converts analog radio frequency (RF) signals received from the base station to digital RF signals using the filtered first master clock signal.

6. The communication system of claim 1, further comprising a remote antenna coupled to at least one of the plurality of fourth modules, wherein the at least one fourth module converts analog RF signals received from the antenna to digital RF signals using the filtered second master clock signal.

7. The communication system of claim 1, wherein the host unit further comprises a backplane coupled between the first module and the plurality of second modules, the backplane configured to distribute the first master clock signal to each of the plurality of second modules.

8. The communication system of claim 1, wherein the remote unit further comprises a plurality of cables, each of the plurality of cables coupled between the third module and one of the plurality of fourth modules, each of the plurality of cables configured to carry the second master clock signal to one of the plurality of fourth modules.

9. The communication system of claim 1, wherein the first converter in each of the plurality of second modules and the second converter in each of the plurality of fourth modules is at least one of a wideband analog-to-digital converter and a wideband digital-to-analog converter.

10. The communication system of claim 1, wherein each of the first oscillator and the second oscillator is a voltage controlled crystal oscillator.

11. The communication system of claim 1, wherein the first filter in each of the plurality of second modules and the second filter in each of the plurality of fourth modules is a monolithic crystal filter.

12. The communication system of claim 1, wherein each of the plurality of second modules and each of the plurality of fourth modules further comprise an amplifier configured to amplify the first master clock signal and the second master clock signal, respectively, and pass the respective amplified master clock signal to the first filter and the second filter, respectively.

13. A unit for use in a communication system, the unit comprising:

a communication module having an oscillator configured to generate a master clock signal having an amplitude-to-noise floor ratio that is insufficient to achieve a desired jitter level;

a plurality of conversion modules; and

a distribution component configured to distribute the master clock signal from the communication module to each of the plurality of conversion modules;

wherein each of the plurality of conversion modules comprises;

a filter configured to filter the master clock signal such that the amplitude to-noise floor ratio is increased sufficiently to achieve the desired jitter level; and

a converter configured to use the filtered master clock signal rather than a clock signal generated in the respective conversion module in converting between analog and digital signals.

14. The unit of claim 13, wherein the communication module is configured to transmit and receive serial data streams.

15. The unit of claim 13, wherein the distribution component comprises one of:

a backplane coupled between the communication module and the plurality of conversion modules, the backplane configured to distribute the master clock signal to each of the plurality of conversion modules; and

a plurality of cables, each of the plurality of cables coupled between the communication module and one of the plurality of conversion modules, each of the plurality of cables configured to carry the master clock signal to one of the plurality of conversion modules.

16. The unit of claim 13, wherein the oscillator is a voltage controlled crystal oscillator.

17. The unit of claim 13, wherein the filter in each of the plurality of conversion modules comprises a monolithic crystal filter.

18. The unit of claim 13, wherein each of the plurality of conversion modules further comprise an amplifier configured to amplify the master clock signal and pass the amplified master clock signal to the filter.

19. A unit for use in a communication system, the unit comprising:

means for generating a master clock signal in a first module, the master clock signal having an amplitude-to-noise floor ratio that is insufficient to achieve a desired jitter level;

means for distributing the master clock signal to a plurality of second modules;

means for filtering the master clock signal in each of the plurality of second modules such that the amplitude to-noise floor ratio is increased sufficiently to achieve the desired jitter level; and

means for converting between digital and analog signals using the filtered master clock signal in each of the plurality of second modules rather than a clock signal generated in each of the respective second modules.

20. The unit of claim 19, further comprising means for amplifying the master clock signal in each of the plurality of second modules, wherein the filtering means filters the amplified master clock signal.

21. A conversion module comprising:

a connector configured to receive a master clock signal having an amplitude-to-noise floor ratio that is insufficient to achieve a desired jitter level;

a filter configured to filter the received master clock signal such that the amplitude to-noise floor ratio is increased sufficiently to achieve the desired jitter level; and

a converter configured to use the filtered master clock signal in converting between analog and digital signals rather than a clock signal generated in the conversion module.

22. The conversion module of claim 21, wherein the filter comprises a monolithic crystal filter.

23. The conversion module of claim 21, further comprising a field programmable gate array (FPGA) which receives the unfiltered master clock signal from the connector.

24. The conversion module of claim 21, further comprising an amplifier configured to amplify the master clock signal and pass the amplified master clock signal to the filter.

25. The conversion module of claim 24 , wherein the amplifier comprises a low noise amplifier.

26. A method of using a master clock signal in a communication unit, the method comprising:

generating the master clock signal in a first module, the master clock signal having an amplitude-to-noise floor ratio that is insufficient to achieve a desired jitter level;

transmitting the master clock signal to each of a plurality of second modules;

filtering the master clock signal in each of the plurality of second modules such that the amplitude to-noise floor ratio is increased sufficiently to achieve the desired jitter level; and

converting between analog and digital signals based on the filtered master clock signal rather than on a clock signal generated in each of the respective second modules.

27. The method of claim 26, wherein transmitting the master clock signal to each of the plurality of second modules comprises transmitting the master clock signal via one of a backplane coupled to each of the plurality of second modules.

28. The method of claim 26, wherein transmitting the master clock signal to each of the plurality of second modules comprises transmitting the master clock signal via a plurality of cables each cable coupled to one of the plurality of second modules.

29. The method of claim 26, further comprising amplifying the master clock signal prior to filtering the master clock signal.

30. The method of claim 26, wherein transmitting the master clock signal comprises transmitting the master clock signal unfiltered to each of the plurality of second modules.