Forward error correction method and communication method, and forward error correction code addition apparatus and communication apparatus

• US 7,669,104 B2
• Filed: 09/06/2005
• Issued: 02/23/2010
• Est. Priority Date: 09/06/2004
• Status: Expired due to Fees

• Current Assignee: Yokogawa Electric Corporation
• Original Assignee: Yokogawa Electric Corporation
• Inventors: Nagashima, Akira, Miura, Akira, Uchida, Isao, Sato, Chie
• Primary Examiner(s): Baker; Stephen M
• Application Number:
  US11/218,440
• Publication Number:
  US 20060053362A1
• Time in Patent Office: 1,631 Days
• Field of Search: 714/755, 714/774
• US Class Current: 714/755
• CPC Class Codes: H03M 13/2909 Product codes
• CPC Class Codes: H03M 13/2912 omitting parity on parity
• CPC Class Codes: H03M 13/6306 Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy H03M13/3761, H03M13/3769 and H03M13/635 take precedence
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/1803 Stop-and-wait protocols
• CPC Class Codes: H04L 1/1867 Arrangements specially adapted for the transmitter end

Abstract

In a forward error correction method and a forward error correction addition apparatus, error correction is performed on the basis of data, to which forward error correction code is added, transmitted through a network to output decoded data. The data transmitted through the network includes information bits represented by an information bit matrix with n rows and m columns (n, m are natural numbers), and redundancy bits represented by an odd number of redundancy information bit rows and an odd number of redundancy information bit columns based on the information bit matrix, which are provided in the row direction and in the column direction of the information bit matrix respectively. The redundancy bits are the forward error correction code.

Claims

1. A communication apparatus, comprising:

an FEC encoder which adds information bits represented by an information bit matrix with n rows and m columns (n, m are natural numbers) to forward error correction code represented by an odd number of redundancy information bit rows and an odd number of redundancy information bit columns based on the information bit matrix, which are provided in the row direction and in the column direction of the information bit matrix respectively;

a packet transmitting section which transmits packets including data in which the forward error correction code is added to the information bits;

a packet receiving section which receives the packets; and

an FEC decoder which performs error correction based on data included in the packets received by the packet receiving section,

wherein the FEC decoder provides a variable degree of reliability for information subjected to error correction.