Partial configuration of a programmable gate array using a bus macro and coupling the third design

• US 7,669,163 B1
• Filed: 01/24/2006
• Issued: 02/23/2010
• Est. Priority Date: 04/26/2001
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Camilleri, Nicolas John, McGettigan, Edward S.
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US11/338,360
• Time in Patent Office: 1,491 Days
• Field of Search: 716/2, 716/11, 716/12, 716/17, 716/19
• US Class Current: 716/138
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A method of partially reconfiguring a field programmable gate array (FPGA) with at least one design that has interdesign routing with at least one other design programmed into the FPGA. A first configuration data set implements a first design in a first area of the FPGA, a second design in a second, non-overlapping area, and at least one bus macro that defines a bus interface between the first design and the second design. The bus interface includes a set of signal lines coupled to the first and second designs and logic that controls input and output of signals over the signal lines. A second configuration data set implements a modified version of the first design in the first area and does not implement any version of the second design. The FPGA is configured with the first configuration data set, and then partially configured with the second configuration data set.

Claims

1. A method for implementing designs on a programmable gate array, comprising:

generating from first and second designs a first configuration data set that implements the first and second designs in first and second areas of the programmable gate array, respectively, wherein the first and second areas do not overlap, and each of the first and second designs includes a bus macro that defines a bus interface between the first and second designs, the bus interface including a set of signal lines coupled to the first and second designs and logic that controls input and output of signals over the signal lines;

configuring the programmable gate array with the first configuration data set;

generating from a third design a second configuration data set that implements the third design in the first area and that does not implement any version of the second design;

wherein the third design is different from the first design and includes the bus macro for coupling the third design to the second design with the set of signal lines; and

partially reconfiguring the programmable gate array with the second configuration data set in the first area,

wherein in the partially reconfigured programmable gate array, the third design implemented with the second configuration data set in the first area is coupled to the set of signal lines.

2. The method of claim 1, wherein generating the first configuration data set includes constraining each bus interface to a particular set of signal lines of the programmable gate array.

3. The method of claim 1, wherein the bus macro in the first design includes a first set of control gates, each control gate having an input coupled to a respective output signal line in the first design and having an output coupled to a respective signal line of the bus interface and adapted to pass the output signal to the signal line responsive to an enable signal from the first design.

4. The method of claim 3, wherein the bus macro in the second design includes a second set of control gates, each control gate having an input coupled to a respective output signal line in the second design and having an output coupled to a respective signal line of the bus interface and adapted to pass the output signal from the second design to the signal line responsive to an enable signal from the second design.

5. The method of claim 1, wherein the steps are performed in the order recited.

6. An apparatus for implementing designs on a programmable gate array, comprising:

means for generating from first and second designs a first configuration data set that implements the first and second designs in first and second areas of the programmable gate array, respectively, wherein the first and second areas do not overlap, and each of the first and second designs includes a bus macro that defines a bus interface between the first and second designs, the bus interface including a set of signal lines coupled to the first and second designs and logic that controls input and output of signals over the signal lines;

means for configuring the programmable gate array with the first configuration data set;

means for generating from a third design a second configuration data set that implements the third design in the first area and that does not implement any version of the second design;

wherein the third design is different from the first design and includes the bus macro for coupling the third design to the second design with the set of signal lines; and

means for partially reconfiguring the programmable gate array with the second configuration data set in the first area;

wherein in the partially reconfigured programmable gate array, the third design implemented with the second configuration data set in the first area is coupled to the set of signal lines that route signals from or to the second design in the second area.