Method and system for efficiently recording processor events in host bus adapters

• US 7,669,190 B2
• Filed: 05/18/2004
• Issued: 02/23/2010
• Est. Priority Date: 05/18/2004
• Status: Expired due to Fees

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: QLogic Corporation (Marvell Technology Group Limited)
• Inventors: Campbell, Frank W., Doan, Tuan A., Konda, Dharma R., Huey, James D.
• Primary Examiner(s): Dam; Tuan Q
• Assistant Examiner(s): Tecklu; Isaac T
• Application Number:
  US10/847,756
• Publication Number:
  US 20050273672A1
• Time in Patent Office: 2,107 Days
• Field of Search: None
• US Class Current: 717/128
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program

Abstract

A host bus adapter (“HBA”) is provided with a programmable trace logic that can be enabled or disabled by firmware running on the HBA and if enabled can receive trace information from at least one processor, which is stored in a local memory buffer controlled by a local memory interface. A receive and transmit path processor data is traced and stored in the local memory buffer. The trace logic includes an arbitration module that receives trace data from plural sources and the trace data is stored in a first in first out based buffer before being sent to a direct memory access arbiter module and then to an external memory. Trace data as stored in the external memory includes a trace data source identity value, and a time stamp value indicating when data was collected.

Claims

1. A system for storing trace information for an adapter coupled to a host computing system, comprising:

a plurality of processing modules in the adapter, each processing module provides a trace information indicative of an operation performed by the processing module;

a programmable trace logic that includes a plurality of trace registers and a temporary memory, and the programmable trace logic configured to selectively enable and disable collection of trace information from the plurality of processing modules by a firmware executed by the adapter;

wherein each of the processing modules is assigned a dedicated trace register from among the plurality of trace registers in the programmable trace logic; and

when the collection of trace information from the plurality of processing modules is selectively enabled for collection by the adapter, the trace information provided by each of the plurality of processing module selectively enabled for collection is temporarily stored in the temporary memory of the programmable trace logic; and

wherein the temporarily stored trace information provided by each of the processing module selectively enabled for collection, a code indicative of the processing module and a time stamp indicative of when the trace information was collected is transferred from the temporary memory to a memory external to the adapter.

2. The system of claim 1, wherein the adapter is a host bus adapter (HBA) and includes a receive path processor as one of the processing modules for processing information received from a storage area network and trace data regarding the receive path processor is first temporarily stored in the temporary memory before being transferred to the external memory.

3. The system of claim 2, wherein the HBA includes a transmit path processor as another processing module to process information received from the host computing system and trace data regarding the transmit path processor is first temporarily stored in the temporary memory before being transferred to the external memory.

4. The system of claim 1, further includes a control register to indicate processing modules that are selectively enabled for collection of trace information.

5. The system of claim 1, wherein the trace logic includes an arbitration module that receives trace data from the plurality of trace registers.

6. The system of claim 1, wherein the trace data is stored in a first in first out (FIFO) based buffer before being sent to a direct memory access arbiter module and then to the external memory.

7. The system of claim 6, wherein trace data as stored in the external memory includes a trace data source identity value, and a time stamp value indicating when trace data was collected.

8. The system of claim 4, wherein trace data from each of the plurality of trace registers is first stored in a first in first out (FIFO) memory location, before being transferred to the memory external to the adapter.

9. The system of claim 8, wherein an arbitration module is used to select one of the trace register from among the plurality of trace registers to transfer data from the selected trace register to the FIFO memory location.

10. A host bus adapter (“

HBA”

) coupled to a host computing system, the HBA having a plurality of processing modules for transferring information to and from the host computing system, comprising;

each processing module configured to provide a trace information indicative of the operation performed by the processing module;

a local memory interface that includes a programmable trace logic that is configured to selectively enable and disable collection of trace information from the plurality of processing modules by a firmware executed by the HBA;

wherein the programmable trace logic includes a plurality of trace registers and a temporary memory; and

each of the processing module is assigned a dedicated trace register from among the plurality of trace registers; and

when, the collection of trace information from the plurality of processing modules is selectively enabled by the adapter, the trace information provided by each of the plurality of processing module selectively enabled for collection is temporarily stored in the temporary memory of the programmable trace logic; and

wherein the temporarily stored trace information provided by each of the processing module selectively enabled for collection, a code indicative of the processing module and a time stamp indicative of when the trace information was collected is transferred to a memory external to the adapter.

11. The HBA of claim 10, includes a receive path processor as one of the processing modules for processing information received from a storage area network and trace data regarding the receive path processor is first temporarily stored in the temporary memory before being transferred to the external memory.

12. The HBA of claim 11, wherein includes a transmit path processor as another processing module to processes information received from the host computing system and trace data regarding the transmit path processor is first temporarily stored in a the temporary memory before being transferred to the external memory.

13. The HBA of claim 10, further includes a control register to indicate processing modules that are selectively enabled for collection of trace information.

14. The HBA of claim 10, wherein the trace logic includes an arbitration module that receives trace data from the plurality of trace registers.

15. The HBA of claim 10, wherein the trace data is stored in a first in first out (FIFO) based buffer before being sent to a direct memory access arbiter module and then to the external memory.

16. The HBA of claim 15, wherein the trace data as stored in the external memory includes a trace data source identity value, and a time stamp value indicating when trace data was collected.

17. The HBA of claim 13, wherein trace data from each of the plurality of trace registers is first stored in a first in first out (FIFO) memory location, before being transferred to the memory external to the adapter.

18. The HBA of claim 17, wherein an arbitration module is used to select a trace register from among the plurality of trace registers to transfer data from the selected trace register to the FIFO memory location.

19. A local memory interface for storing processor trace information for an adapter coupled to a host computing system, the adapter using a plurality of processing modules transferring information to and from the host computing system, comprising:

a programmable trace logic that includes a plurality of trace registers and a temporary memory;

wherein the programmable trace logic is configured to receive from each processing module a trace information indicative of the operation performed by the processing module;

wherein the programmable trace logic is configured to selectively enable and disable collection of trace information from the plurality of processing modules by a firmware executed by the adapter;

wherein each of the processing modules is assigned a dedicated trace register from among the plurality of trace registers; and

when the collection of trace information from the plurality of processing modules is selectively enabled by the adapter, the trace information received from each of the plurality of processing module selectively enabled for collection is temporarily stored in the temporary memory; and

wherein the temporarily stored trace information received from each of the processing module, a code indicative of the processing module and a time stamp indicative of when the trace information was collected is transferred from the temporary memory to a memory external to the adapter.

20. The interface of claim 19, wherein the trace logic includes an arbitration module that receives trace data from the plurality of trace registers.

21. The interface of claim 20, wherein the trace data is stored in a first in first out (FIFO) based buffer before being sent to a direct memory access arbitration module and then to the external memory.

22. The interface of claim 19, wherein trace data as stored in the external memory includes a trace data source identity value, and a time stamp value indicating when trace data was collected.