Methods for verifying correct counter-bore depth and precision on printed circuit boards

• US 7,669,321 B1
• Filed: 03/14/2006
• Issued: 03/02/2010
• Est. Priority Date: 07/13/2005
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Martin, John, Levy, John Benjamin, Pakravan, Farhad
• Primary Examiner(s): PHAN, THIEM D
• Application Number:
  US11/375,435
• Time in Patent Office: 1,449 Days
• Field of Search: 298/52, 294/020.1, 294/020.6, 294/070.1, 298/25, 174/260, 174/261, 361/784, 361/790, 408/1.R, 408/12, 408/13
• US Class Current: 29/852
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing
• CPC Class Codes: H05K 2203/0207 Partly drilling through substrate until a controlled depth, e.g. with end-point detection
• CPC Class Codes: H05K 2203/175 Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
• CPC Class Codes: H05K 3/0047 Drilling of holes
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49718 Repairing
• CPC Class Codes: Y10T 29/49726 Removing material
• CPC Class Codes: Y10T 29/49764 with testing or indicating
• CPC Class Codes: Y10T 408/03 Processes
• CPC Class Codes: Y10T 408/173 Responsive to work
• CPC Class Codes: Y10T 408/175 to control relative positioning of Tool and work

Abstract

A test site is incorporated on a circuit board having a set of test connections passing through a test via on respective test connection layer, the test connection layers including (1) a first layer adjacent to a target layer, and (2) a second layer spaced apart from the target layer with the first layer therebetween. The test via is back-drilled from the direction of the second layer to remove undesired via metallization, breaking the test connections of all the layers through which it passes, and the continuity of the test connections is measured to determine a pattern of broken and non-broken test connections resulting from the back-drilling. The pattern of broken and non-broken test connections is examined to ascertain the actual depth of the back-drilling in relation to the target layer.

Claims

1. A method of manufacturing a set of identical multiple-layer circuit boards, comprising:

incorporating a test site on each of the set of circuit boards, the test site having a set of test connections passing through a test via on respective test connection layers of each of the set of circuit boards, the set of test connections including a first test connection, a second test connection, and a third test connection, the test connection layers including (1) a first layer adjacent to a target layer, (2) a second layer spaced apart from the target layer with the first layer therebetween, and (3) a third layer spaced apart from the target layer with the first layer and second layer therebetween;

wherein the first layer includes a first test connection point, the second layer includes a second test connection point, the third layer includes a third test connection point, and the first test connection layer, the second test connection layer, the third test connection layer are short circuited to a common test connection point,

wherein the first test connection point, the second test connection point, the third test connection point, and a common test connection point surround the test via,

wherein the first test connection is a first conductive pathway from the first test connection point, through the test via, to the common test connection point,

wherein the second test connection is a second conductive pathway from the second test connection point, through the test via, to the common test connection point, and

wherein the third test connection is a third conductive pathway from the third test connection point, through the test via, to the common test connection point;

back-drilling, on a first circuit board of the set of circuit boards, with a back-drill the test via from the direction of the third layer to remove undesired via metallization, the back-drilling breaking the test connections of all the layers through which it passes;

measuring, on the first circuit board, the continuity of the test connections to determine a pattern of broken and non-broken test connections resulting from the back-drilling; and

examining, on the first circuit board, the pattern of broken and non-broken test connections to ascertain the actual depth of the back-drilling of the test via in relation to the target layer;

wherein the method further comprising;

in response to examining, on the first circuit board, the pattern of broken and non-broken test connections, adjusting the back-drill based on the ascertained actual depth of the back drilling of the test via in relation to the target layer, and

back-drilling with the adjusted back-drill the test via of a second circuit board of the set of circuit boards;

wherein back-drilling, on the first circuit board, with a back-drill the test via from the direction of the third layer to remove undesired via metallization breaks the third test connection of all the third layer, the second test connection of the second layer, and the first test connection of the first layer;

wherein measuring, on the first circuit board, the continuity of the test connections to determine a pattern of broken and non-broken test connections resulting from the back-drilling determines that the third test connection, the second test connection, and the first test connection are broken;

wherein examining, on the first circuit board, the pattern of broken and non-broken test connections to ascertain the actual depth of the back-drilling of the test via in relation to the target layer determines that undesired via metallization has been removed and that the target layer may have been nicked; and

wherein adjusting the back-drill based on the ascertained actual depth of the back drilling of the test via in relation to the target layer includes adjusting the back-drill to drill shallower.

2. A method according to claim 1, wherein the first layer is a must-not-cut layer serving to protect connections on the target layer from being partially broken by the back-drilling, and wherein examining the pattern of broken and non-broken test connections comprises determining whether a test connection on the must-not-cut layer is non-broken.

3. A method according to claim 2, wherein the first layer is immediately adjacent the target layer with no other conductive layers therebetween.

4. A method according to claim 2, wherein the first layer is spaced apart from the target layer with at least one other conductive layer therebetween.

5. A method according to claim 1, wherein the second layer is a must-cut layer serving to establish a minimum back-drilling depth, and wherein examining the pattern of broken and non-broken test connections comprises determining whether a test connection on the must-cut layer is broken.

6. A method according to claim 1, wherein the test connections of the test site include test connections passing through the test via on respective additional test connection layers disposed between the first and second layers.

7. A method according to claim 1, wherein the test site is one of plurality of similar test sites incorporated at respective different locations on each of the set of circuit boards.

8. A method according to claim 1, wherein the target layer is a first target layer at a first depth of the circuit board and the test connections, test via, test connection layers, and pattern of broken and non-broken connections are first site test connections, a first test via, first test connection layers, and a first pattern of broken and non-broken connections pertaining to the first target layer, and wherein the incorporating, back-drilling, measuring and examining are all repeated for respective second site test connections, second test via, second test connection layers and second pattern of broken and non-broken connections pertaining to a second target layer at a second depth of each of the set of circuit boards.

9. A method according to claim 8, wherein the first and second site test connections are immediately adjacent to each other so as to form part of the test site.

10. A method according to claim 8, wherein the first target layer is relatively shallow and the second target layer is relatively deep, and wherein the spacing between the first and second layers of the first site test connection layers is greater than the spacing between the first and second layers of the second site test connection layers.

11. The method according to claim 1, wherein the target layer includes the normal functional circuitry of the board, and the test connection layers include test circuitry that is independent of the normal functional circuitry of the board.

12. A method of manufacturing a set of identical multiple-layer circuit boards, comprising:

incorporating a test site on each of the set of circuit boards, the test site having a set of test connections passing through a test via on respective test connection layers of each of the set of circuit boards, the set of test connections including a first test connection, a second test connection, and a third test connection, the test connection layers including (1) a first layer adjacent to a target layer, (2) a second layer spaced apart from the target layer with the first layer therebetween, and (3) a third layer spaced apart from the target layer with the first layer and second layer therebetween;

wherein the first layer includes a first test connection point the second layer includes a second test connection point, the third layer includes a third test connection point, and the first test connection layer, the second test connection layer, the third test connection layer are short circuited to a common test connection point,

wherein the first test connection point, the second test connection point, the third test connection point, and a common test connection point surround the test via,

wherein the first test connection is a first conductive pathway from the first test connection point, through the test via, to the common test connection point,

wherein the second test connection is a second conductive pathway from the second test connection point, through the test via, to the common test connection point, and

wherein the third test connection is a third conductive pathway from the third test connection point, through the test via, to the common test connection point;

back-drilling, on a first circuit board of the set of circuit boards, with a back-drill the test via from the direction of the third layer to remove undesired via metallization, the back-drilling breaking the test connections of all the layers through which it passes;

measuring, on the first circuit board, the continuity of the test connections to determine a pattern of broken and non-broken test connections resulting from the back-drilling; and

examining, on the first circuit board, the pattern of broken and non-broken test connections to ascertain the actual depth of the back-drilling of the test via in relation to the target layer;

wherein the method further comprising;

in response to examining, on the first circuit board, the pattern of broken and non-broken test connections, adjusting the back-drill based on the ascertained actual depth of the back drilling of the test via in relation to the target layer, and

back-drilling with the adjusted back-drill the test via of a second circuit board of the set of circuit boards;

wherein back-drilling, on the first circuit board, with a back-drill the test via from the direction of the third layer to remove undesired via metallization breaks the third test connection of the third layer and the second test connection of the second layer;

wherein measuring, on the first circuit board, the continuity of the test connections to determine a pattern of broken and non-broken test connections resulting from the back-drilling determines that the third test connection and the second test connection are broken and that the first test connection is not broken;

wherein examining, on the first circuit board, the pattern of broken and non-broken test connections to ascertain the actual depth of the back-drilling of the test via in relation to the target layer determines that undesired via metallization has been removed and that the target layer has not been nicked; and

wherein adjusting the back-drill based on the ascertained actual depth of the back drilling of the test via in relation to the target layer includes adjusting the back-drill to maintain current drill depth.