Method and structure for forming an integrated spatial light modulator

• US 7,670,880 B2
• Filed: 02/01/2007
• Issued: 03/02/2010
• Est. Priority Date: 01/03/2005
• Status: Active Grant

• Current Assignee: Miradia Inc. (Walsin Lihwa Corporation)
• Original Assignee: Miradia Inc. (Walsin Lihwa Corporation)
• Inventors: Huang, Kegang, Yang, Xiao, Chen, Dongmin
• Primary Examiner(s): Cao; Phat X
• Assistant Examiner(s): Doan; Nga
• Application Number:
  US11/670,362
• Publication Number:
  US 20070128771A1
• Time in Patent Office: 1,125 Days
• Field of Search: 438/125, 438/57
• US Class Current: 438/125
• CPC Class Codes: G02B 26/0841 the reflecting element being moved or deformed by electrostatic means

Abstract

A method of fabricating an integrated spatial light modulator. The method includes providing a first substrate including a bonding surface and processing a device substrate to form at least an electrode layer. The method also includes depositing a first portion of a multi-layer standoff layer on the electrode layer, depositing a second portion of the multi-layer standoff layer on the first portion of the multi-layer standoff layer, and forming electrically insulating standoff structures from the multi-layer standoff layer. The method further includes joining the bonding surface of the first substrate to the standoff structures on the device substrate, thinning the first substrate, patterning the first substrate to form a mask, and forming a plurality of moveable structures from the first substrate. The moveable structures are aligned with at least one of the plurality of electrodes and adapted to rotate with respect to the standoff structures.

Claims

1. A method of fabricating an integrated spatial light modulator, the method comprising:

providing a first substrate including a bonding surface;

processing a device substrate to form at least an electrode layer, the electrode layer including a plurality of electrodes;

depositing a first electrically insulating portion of a multi-layer standoff layer on the electrode layer;

depositing a second electrically insulating portion of the multi-layer standoff layer on the first electrically insulating portion of the multi-layer standoff layer;

forming standoff structures from the multi-layer standoff layer;

joining the bonding surface of the first substrate to the standoff structures on the device substrate;

thinning the first substrate;

patterning the first substrate to form a mask; and

forming a plurality of moveable structures from the first substrate, at least one of the plurality of moveable structures aligned with at least one of the plurality of electrodes and adapted to rotate with respect to the standoff structures.

2. The method of claim 1 further comprising, after the step of depositing the second electrically insulating portion of the multi-layer standoff layer, performing chemical mechanical polishing of the second portion of the multi-layer standoff layer to planarize an upper surface of the second electrically insulating portion of the multi-layer standoff layer.

3. The method of claim 1 wherein the first substrate is a silicon on insulator substrate.

4. The method of claim 3 wherein thinning the first substrate comprises removing a first silicon layer of the silicon on insulator substrate and a buried oxide layer of the silicon on insulator substrate to expose a second semi-transparent silicon layer.

5. The method of claim 1 wherein at least one of the first electrically insulating portion of the multi-layer standoff layer or the second electrically insulating portion of the multi-layer standoff structure is fabricated from silicon oxide.

6. The method of claim 1 wherein at least one of the first electrically insulating portion of the multi-layer standoff layer or the second electrically insulating portion of the multi-layer standoff structure is fabricated from silicon nitride.

7. The method of claim 1 wherein at least one of the first electrically insulating portion of the multi-layer standoff layer or the second electrically insulating portion of the multi-layer standoff structure is deposited using a low temperature deposition process performed at a temperature of less than 400°

C.

8. The method of claim 7 wherein the device substrate comprises CMOS circuitry.

9. The method of claim 1 wherein the standoff structures have a height of between 0.5 μ

m and 2.5 μ

m.

10. The method of claim 1 wherein forming standoff structures from the multi-layer standoff layer comprises etching the multi-layer standoff layer to form the standoff structures.

11. The method of claim 1 wherein the step of joining is performed using an alignment process with a tolerance requirement of less than 1 cm.

12. The method of claim 11 wherein the step of joining comprises forming a covalent bond at room temperature.

13. The method of claim 12 wherein the step of joining further comprises a plasma activation process and a room temperature covalent bonding process.

14. A method of fabricating an integrated spatial light modulator, the method comprising:

providing a first substrate including a bonding surface;

processing a device substrate to form at least an electrode layer, the electrode layer including a plurality of electrodes;

depositing an electrically insulating standoff layer on the electrode layer;

forming electrically insulating standoff structures from the standoff layer, wherein the standoff structures are characterized by a height of between 0.5 μ

m and 2.5 μ

m;

joining the bonding surface of the first substrate to the standoff structures on the device substrate;

thinning the first substrate;

patterning the first substrate to form a mask; and

forming a plurality of moveable structures from the first substrate, at least one of the plurality of moveable structures aligned with at least one of the plurality of electrodes and adapted to rotate at least with respect to the standoff structures.

15. The method of claim 14 wherein the at least one of the plurality of moveable structures is adapted to rotate by an angle of ±

12°

.

16. The method of claim 15 wherein the at least one of the plurality of moveable structures is adapted to rotate by an angle of ±

13°

.

17. The method of claim 16 wherein the at least one of the plurality of moveable structures is adapted to rotate by an angle of ±

14°

.

18. The method of claim 14 further comprising, after the step of depositing a electrically insulating standoff layer, performing chemical mechanical polishing of the electrically insulating standoff layer to planarize an upper surface of the electrically insulating standoff layer.

19. The method of claim 14 wherein the first substrate is a silicon on insulator substrate.

20. The method of claim 14 wherein the electrically insulating standoff layer comprises at least one of silicon oxide or silicon nitride.

21. The method of claim 14 wherein the device substrate comprises CMOS circuitry.

22. The method of claim 14 wherein forming standoff structures from the standoff layer comprises etching the electrically insulating standoff layer to form the standoff structures.

23. The method of claim 14 wherein the step of joining comprises forming a covalent bond at room temperature.

24. The method of claim 23 wherein the step of joining further comprises a plasma activation process and a room temperature covalent bonding process.