Configuration of high-voltage semiconductor power device to achieve three dimensional charge coupling

• US 7,670,908 B2
• Filed: 01/22/2007
• Issued: 03/02/2010
• Est. Priority Date: 01/22/2007
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Feng, Tao, Hebert, Francois
• Primary Examiner(s): Monbleau; Davienne
• Assistant Examiner(s): Rodela; Eduardo A
• Application Number:
  US11/656,104
• Publication Number:
  US 20080173969A1
• Time in Patent Office: 1,135 Days
• Field of Search: 438/488, 438/239, 438/243, 438/246, 438/247, 438/248, 438/259, 438/270, 438/589, 438/592, 438/593, 257/329, 257/330, 257/301, 257/304, 257/311, 257/488, 257/E27.016, 257/E27.034, 257/E27.092, 257/E21.008, 257/E29.13, 257/E29.621, 257/E29.624
• US Class Current: 438/259
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path.

Claims

1. A method for manufacturing a semiconductor device comprising:

forming a trench with insulated sidewalls extending from a top region through an intermediate region toward a bottom region to provide a controllable current path traversing through said intermediate region; and

filling said trench with a dielectric followed by forming nano-nodules as charge-islands to distribute substantially uniformly over an entire volume of said dielectric in said trench for electrically coupling with said intermediate region for continuously and uniformly distributing a voltage drop through said current path.

2. The method of claim 1 wherein:

said step of filling said trench with said dielectric further comprising steps of implanting Si ions into said entire volume of said dielectric in said trench followed by an annealing process to form said nano-nodules as said charge-islands to distribute substantially uniformly over an entire volume of said dielectric in said trench.

3. The method of claim 1 wherein:

said step of filling said trench with said dielectric further comprising steps of implanting Ge ions into said entire volume of said dielectric in said trench followed by an annealing process to form said nano-nodules as said charge-islands to distribute substantially uniformly over an entire volume of said dielectric in said trench.

4. The method of claim 1 wherein:

said step of filling said insulating trench with said dielectric further comprising steps of implanting semiconductor ions into said entire volume of said dielectric in said trench followed by an annealing process to form said nano-nodules as said charge-islands to distribute substantially uniformly over an entire volume of said dielectric in said trench.

5. The method of claim 1 wherein:

said step of filling said trench with said dielectric further comprising a step of depositing semiconductor nano-crystals with oxide shells by applying an aerosol process to form said nano-nodules as said charge-islands to distribute substantially uniformly over an entire volume of said dielectric in said trench.

6. The method of claim 1 wherein:

said step of filling said trench with said dielectric further comprising steps of depositing a conductive material with said dielectric into said trench followed by inducing a nucleation on said conductive material to form said nano-nodules as said charge-islands to distribute substantially uniformly over an entire volume of said dielectric in said trench.

7. The method of claim 1 wherein:

said step of filling said trench with said dielectric further comprising steps of depositing a semiconductor material with said dielectric into said trench followed by inducing a nucleation on said semiconductor material to produce grains in said semiconductor material as said nano-nodules to distribute as charge-islands substantially uniformly over an entire volume of said dielectric in said trench.

8. The method of claim 1 wherein:

said step of filling said trench with said dielectric further comprising steps of depositing a silicon with said dielectric into said trench followed by inducing a nucleation on said silicon to produce grains in said silicon as said nano-nodules to distribute as charge-islands substantially uniformly over an entire volume of said dielectric in said trench.

9. The method of claim 1 wherein:

said step of filling said trench with said dielectric further comprising steps of depositing a polysilicon as said dielectric into said trench followed by steps of doping and annealing of said polysilicon in said trench for inducing to produce grains in said polysilicon as said nano-nodules to distribute as charge-islands substantially uniformly over an entire volume of said dielectric in said trench.

10. The method of claim 1 wherein:

said step of filling said trench with said dielectric further comprising steps of filling said trench with said dielectric with embedded semiconductor nodules into said trench to distribute said embedded semiconductor nodules as charge-islands substantially uniformly over an entire volume of said dielectric in said trench.

11. The method of claim 1 wherein:

said step of filling said trench with said dielectric further comprising steps of applying an annealing process to said dielectric material filling in said trench to form said nano-nodules as charge-islands substantially uniformly over an entire volume of said dielectric in said trench.

12. The method of claim 1 wherein:

said step of filling said trench with said dielectric further comprising steps of depositing seed layers in said dielectric in said trench followed by applying a grain formation process to form said nano-nodules as charge-islands substantially uniformly over an entire volume of said dielectric in said trench.

13. The method of claim 1 wherein:

said step of filling said trench with said dielectric further comprising steps of depositing a polysilicon as said dielectric into said trench followed by applying a nucleating process to form separated silicon grains as said nano-nodules to distribute as charge-islands substantially uniformly over an entire volume of said dielectric in said trench.

14. The method of claim 1 wherein:

said step of filling said trench with said dielectric further comprising steps of filling said dielectric in said trench with aerosol silicon nano-crystals as said nano-nodules to distribute as charge-islands substantially uniformly over an entire volume of said dielectric in said trench.