Method of fabricating strain-silicon CMOS

• US 7,670,923 B1
• Filed: 08/28/2008
• Issued: 03/02/2010
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Nayak, Deepak Kumar, Luo, Yuhao
• Primary Examiner(s): Ghyka; Alexander G
• Assistant Examiner(s): Nikmanesh; Seahvosh J
• Application Number:
  US12/200,871
• Time in Patent Office: 551 Days
• Field of Search: 438/478, 438/269, 438/413, 257/E21.403, 257/E21.632
• US Class Current: 438/413
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Recesses are formed in the drain and source regions of an MOS transistor. The recesses are formed using two anisotropic etch processes and first and second sidewall spacers. The recesses are made up of first and second recesses, and the depths of the first and second recesses are independently controllable. The recesses are filled with a stressed material to induce strain in the channel, thereby improving carrier mobility. The widths and depths of the first and second recesses are selectable to optimize strain in the channel region.

Claims

1. A method of manufacturing a metal-oxide-semiconductor (“

MOS”

) transistor comprising;

forming first sidewall spacers on the sides of a gate of the MOS transistor;

performing a first anisotropic silicon etch in source and drain regions of the MOS transistor so as to form first recesses;

depositing a second sidewall film on the MOS transistor;

forming second sidewall spacers;

performing a second anisotropic silicon etch in the source and drain regions of the MOS transistor so as to form second recesses, combined recesses being formed from at least the first recesses and the second recesses;

removing the second sidewall spacers; and

forming stressed material in the combined recesses.

2. The method of claim 1 wherein the step of forming stressed material comprises selective epitaxial growth of stressed material.

3. The method of claim 1 wherein the step of forming stressed material comprises forming doped stressed material and further comprising a step of thermally treating the MOS transistor so as to drive in dopant from the doped stressed material to form extension regions of the MOS transistor.

4. The method of claim 1 wherein a first recess has a first depth between 20 nm and 50 nm, and a combined recess has a combined depth between 70 nm and 200 nm.

5. The method of claim 1 wherein the step of performing the first anisotropic silicon etch follows the step of forming second sidewall spacers and the step of removing the second sidewall spacers precedes the step of performing a second anisotropic silicon etch.

6. The method of claim 1 wherein the first recesses are self-aligned to the first sidewall spacers and the second recesses are self-aligned to the second sidewall spacers.

7. The method of claim 1 wherein the first recesses are self-aligned to the second sidewall spacers and the second recesses are self-aligned to the first sidewall spacers.

8. A method of fabricating a metal-oxide-semiconductor (“

MOS”

) transistor in a complementary MOS (“

CMOS”

) cell having a first-conductivity-type MOS portion and a second-conductivity-type MOS portion comprising;

forming first sidewall spacers on sides of a first gate of the first-conductivity-type MOS portion and on sides of a second gate of the second-conductivity-type MOS portion;

performing lightly-doped drain and halo implants on the first-conductivity-type MOS portion;

patterning photoresist over the first-conductivity-type MOS portion;

performing a first anisotropic selective etch in exposed source/drain areas of the second-conductivity-type MOS portion so as to form first recesses;

depositing a second sidewall film over at least the first sidewall spacers on the sides of the second gate;

forming second sidewall spacers on at least the second gate;

depositing an epitaxial mask film over the CMOS cell;

removing the epitaxial mask film from the second-conductivity-type MOS portion;

performing a second anisotropic selective etch in source/drain regions to form second recesses, the second recesses and first recesses forming combined recesses;

removing the second sidewall spacers from the second gate; and

forming stressed material in the combined recesses.

9. The method of claim 8 wherein the stressed material is selective epitaxial growth (“

SEG”

) SiGe.

10. The method of claim 8 wherein the stressed material is doped.

11. The method of claim 10 further comprising a step of thermally treating the second-conductivity-type MOS portion to drive in and activate dopant in semiconductor material proximate to the stressed material.