Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing

• US 7,671,362 B2
• Filed: 12/10/2007
• Issued: 03/02/2010
• Est. Priority Date: 12/10/2007
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc., GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc., International Business Machines Corporation
• Inventors: Werking, James, Grunow, Stephan, Standaert, Theodorus E., Sankaran, Sujatha, Simon, Andrew H., McLaughlin, Paul S., Filippi, Ronald G., Bolom, Tibor, Chanda, Kaushik
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): CAMPBELL, SHAUN M
• Application Number:
  US11/953,568
• Publication Number:
  US 20090146143A1
• Time in Patent Office: 813 Days
• Field of Search: 257/48, 257E21521-E21531, 428/14, 324512-769
• US Class Current: 257/48
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.

Claims

1. A test structure for integrated circuit (IC) device fabrication, the structure comprising:

a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; and

each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the deposition process conditions, wherein a top portion of each of the one or more vias has at least one chamfer surface at one side thereof and a substantially straight vertical sidewall profile at an opposing side thereof such that a chamfer angle defined by the at least one chamfer surface of the one or more vias varies from chain to chain so as to produce the variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.

2. The test structure of claim 1, wherein the at least one chamfer surface comprises a first chamfer surface oriented in a first direction parallel to a planar surface of the IC wafer and a second chamfer surface oriented in a second direction parallel to the planar surface of the IC wafer, the first direction orthogonal to the second direction.

3. The test structure of claim 1, wherein each of the plurality of test structure chains further comprises:

a first metal line formed at a first metal level directly below the one or more vias, and adjacent the one side of the one or more vias corresponding to the at least one chamfer surface; and

a second metal line formed at the first metal level directly below the one or more vias, and adjacent the opposite side of the one or more vias corresponding to the substantially straight vertical sidewall profile;

wherein the first and second metal lines are configured to compare leakage currents from the one side of the one or more vias corresponding to the at least one chamfer surface and the opposite side of the one or more vias corresponding to the substantially straight vertical sidewall profile.

4. The test structure of claim 3, wherein the chamfer angle defined by the at least one chamfer surface of the one or more vias is dependent upon the geometry of one or more line openings corresponding to the conductive lines disposed above the one or more vias at a second metal level directly above the one or more vias.

5. The test structure of claim 4, wherein each of the plurality of test structure chains further comprises a pair of metal lines formed at a third metal above the second metal level, the pair of metal lines formed at opposing ends of the chain, wherein the pair of metal lines are configured to implement a series resistance measurement of the one or more vias.

6. The test structure of claim 1, wherein the one or more vias and the conductive line comprise a material selected from the group of:

copper (Cu), aluminum (Al), gold (Au), silver (Ag), alloys and combinations thereof.

7. The test structure of claim 1, wherein the liner layer thickness corresponds to a liner layer comprising a material selected from the group of:

tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), and combinations thereof.