Semiconductor layer structure and method of making the same

• US 7,671,371 B2
• Filed: 06/30/2008
• Issued: 03/02/2010
• Est. Priority Date: 06/21/2004
• Status: Expired due to Fees

• Current Assignee: BeSang Inc.
• Original Assignee: Sang-Yun Lee
• Inventors: Lee, Sang-Yun
• Primary Examiner(s): Tran; Long K
• Application Number:
  US12/165,445
• Publication Number:
  US 20080265360A1
• Time in Patent Office: 610 Days
• Field of Search: 257/13, 257/79, 257/591, 257/928, 257/E27.011, 257/E27.02, 257/E21.088, 257/E21.122, 257/347, 257/351, 257/E29.287
• US Class Current: 257/79
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01093 : Neptunium [Np]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass
• CPC Class Codes: Y10S 257/928 : with shorted PN or schottky junction other than emitter junction

Abstract

A semiconductor layer structure includes a donor substrate and a detach region carried by the donor substrate. A device structure is carried by the donor substrate and positioned proximate to the detach region. The device structure includes a stack of crystalline semiconductor layers. The stack of crystalline semiconductor layers includes a pn junction.

Claims

1. Apparatus, comprising:

a donor substrate;

a device structure carried by the donor substrate, the device structure including a stack of crystalline semiconductor layers,

wherein the stack of crystalline semiconductor layers includes a semiconductor layer with a graded doping concentration;

a detach region which extends between the donor substrate and device structure; and

wherein the detach region includes a dielectric material.

2. The apparatus of claim 1, wherein the device structure includes a p-n junction.

3. The apparatus of claim 1, wherein the device structure includes an intrinsically doped layer.

4. The apparatus of claim 1, wherein the device structure includes alternately doped semiconductor layers.

5. The apparatus of claim 1, wherein the device structure includes a first layer of a first conductivity type positioned between second and third layers of opposite conductivity types, the doping concentration of the first layer near the second layer being different from the doping concentration of the first layer near the third layer.

6. The apparatus of claim 1, wherein the device structure includes a first layer of a first conductivity type positioned between second and third layers of opposite conductivity types, the detach region being positioned near the third layer and the doping concentration of the third layer near the detach region being different than the doping concentration of the third layer near the first layer.

7. The apparatus of claim 1, wherein the device structure includes a first layer of a first conductivity type positioned between second and third layers of opposite conductivity types, the doping concentration of the first layer near the second layer being substantially the same as the doping concentration of the first layer near the third layer.

8. The apparatus of claim 1, wherein the detach region includes at least one of a dielectric material region, a hydrogen doped region, and a porous region.

9. The apparatus of claim 1, wherein the device structure includes single crystalline semiconductor material.

10. Apparatus, comprising:

a semiconductor substrate;

a detach region carried by the semiconductor substrate; and

a stack of crystalline silicon semiconductor layers carried by the semiconductor substrate,

wherein the detach region extends between the semiconductor substrate and stack of crystalline silicon semiconductor layers,

wherein the stack of crystalline silicon semiconductor layers has a graded doping concentration proximate to the detach region.

11. The apparatus of claim 10, wherein the semiconductor substrate includes single crystalline semiconductor material.

12. The apparatus of claim 10, wherein the detach region includes a dielectric material layer.

13. The apparatus of claim 10, wherein the detach region includes a porous material layer.

14. The apparatus of claim 10, wherein the stack of doped semiconductor layers includes an npn layer structure.

15. The apparatus of claim 10, wherein the stack of crystalline semiconductor layers includes a pnp layer structure.

16. Apparatus, comprising:

a donor substrate;

a detach region carried by the donor substrate; and

a device structure carried by the donor substrate and positioned proximate to the detach region, the device structure including a stack of crystalline semiconductor layers;

wherein the stack has a graded doping concentration proximate to the detach region;

wherein the detach region includes a porous material layer which extends between the donor substrate and device structure.

17. The apparatus of claim 16, wherein the stack of crystalline semiconductor layers includes a p-n junction.

18. The apparatus of claim 16, wherein the stack of crystalline semiconductor layers are blanket layers of semiconductor material.

19. The apparatus of claim 16, further including a metal layer positioned on the device structure.

20. The apparatus of claim 16, wherein the donor substrate consists of semiconductor material.