Pixel having two semiconductor layers, image sensor including the pixel, and image processing system including the image sensor

• US 7,671,435 B2
• Filed: 09/21/2006
• Issued: 03/02/2010
• Est. Priority Date: 09/29/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ahn, Jung-Chak
• Primary Examiner(s): Landau; Matthew C
• Assistant Examiner(s): Chan; Candice Y
• Application Number:
  US11/524,695
• Publication Number:
  US 20070069258A1
• Time in Patent Office: 1,258 Days
• Field of Search: 257/292, 257/444, 257/E31.058, 257/31.063, 257/31.115, 257/25.032, 257 27133-136, 257/27.139
• US Class Current: 257/444
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers

Abstract

An image sensor having pixels that include two patterned semiconductor layers. The top patterned semiconductor layer contains the photoelectric elements of pixels having substantially 100% fill-factor. The bottom patterned semiconductor layer contains transistors for detecting, resetting, amplifying and transmitting signals charges received from the photoelectric elements. The top and bottom patterned semiconductor layers may be separated from each other by an interlayer insulating layer that may include metal interconnections for conducting signals between devices formed in the patterned semiconductor layers and from external devices.

Claims

1. An image sensor comprising:

a first patterned semiconductor layer;

a second patterned semiconductor layer;

and an interlayer insulating layer interposed between the first patterned semiconductor layer and the second patterned semiconductor layer;

a photodiode, having an N-type region and a P-type region, wherein the P-type region envelops the N-type region, formed in the second patterned semiconductor layer; and

at least one transistor formed in the first patterned semiconductor layer.

2. The image sensor as set forth in claim 1, wherein the at least one transistor formed in the first patterned semiconductor layer is electrically connected to the photodiode and sensing signal charges generated in the photodiode.

3. The image sensor as set forth in claim 1, wherein the photodiode comprises a PN junction at the interface of the N-type region and the P-type region.

4. The image sensor as set forth in claim 3, wherein the P-type region enveloping the N-type region has substantially the same doping amount of a p-type dopant at the entire PN junction.

5. The image sensor as set forth in claim 1, further comprising:

first and second charge collection regions formed in the second and first semiconductor patterns respectively, electrically connected to each other, for accepting the signal charges generated in the photodiode,

wherein the at least one transistor is electrically connected to the first and second charge collection regions.

6. The image sensor as set forth in claim 5, wherein the at least one transistor electrically connected to the first and second charge collection regions comprises:

a first transistor for sensing signal charges of the first and second charge collection regions; and

a second transistor for resetting signal charges of the first and second charge collection regions;

wherein the first and second transistors are electrically connected to each other through a common drain,

wherein a gate of the first transistor is electrically connected to the first and second charge collection regions, and

wherein the first charge collection region acts as a source of the second transistor.

7. The image sensor as set forth in claim 6, further comprising:

a transfer transistor formed in the second patterned semiconductor layer for transferring the signal charges to the second charge collection region from the photodiode, wherein the gate of the transfer transistor is formed in the second patterned semiconductor layer.

8. The image sensor as set forth in claim 5, further comprising:

a transfer transistor formed in the second patterned semiconductor layer for transferring the signal charges from the photodiode to the first and second charge collection regions, wherein the gate of the transfer transistor is formed in the second patterned semiconductor layer.

9. The image sensor as set forth in claim 1, wherein the P-type region formed in the second patterned semiconductor layer and the insulator on the gate of a field effect transistor formed in the second patterned semiconductor layer completely encapsulate the N-type region.

10. The image sensor as set forth in claim 5, wherein the second charge collection region is formed in the P-type region apart from the N-type region.

11. The image sensor as set forth in claim 1, further comprising a color filter formed directly on the second patterned semiconductor layer.

12. The image sensor as set forth in claim 1, wherein the N-type region is lightly doped with an N-type dopant, and the P-type region enveloping the N-type region is lightly doped with an N-type dopant.

13. The image sensor as set forth in claim 1, wherein the P-type region enveloping the N-type region is doped with approximately the same P-type dopant amount on the entire PN junction thereof.

14. The image sensor as set forth in claim 1, wherein the N-type region is enveloped by the P-type region being approximately homogeneously doped with approximately the same amount of P-type dopant.

15. The image sensor as set forth in claim 1, wherein the top of the N-type region consists essentially of a substantially planar horizontal PN junction, and the bottom of the N-type region interfaces the P-type region by at least one substantially planar horizontal PN interface.

16. The image sensor as set forth in claim 15, wherein the N-type region is substantially square having an approximately planar vertical PN interface on each of four sides.

17. The image sensor as set forth in claim 15, wherein the bottom of the N-type region comprises a substantially planar interface with an insulator.

18. The image sensor as set forth in claim 1, wherein the first semiconductor pattern includes a reset gate, a source follower gate, and a selection gate, and is disposed under the second semiconductor pattern and is entirely covered by the N-type region.

19. The image sensor as set forth in claim 1, wherein the interlayer insulating layer includes metal interconnections for applying voltages to the gate of a transfer transistor formed in the second patterned semiconductor layer and to a source of the reset transistor formed in the first patterned semiconductor layer.

20. An image sensor comprising:

a photodiode having an N-type semiconductor region and a P-type semiconductor region, wherein the P-type region envelops the N-type region,

wherein the N-type region is formed in a second patterned semiconductor layer; and

the P-type region enveloping the N-type region is formed in the second patterned semiconductor layer,

wherein the photodiode is formed in the second patterned semiconductor layer, and further comprising;

a first patterned semiconductor layer formed below the second patterned semiconductor layer;

a transfer transistor formed in the second patterned semiconductor layer for transferring signal charges from the photodiode to a second charge collection region in the first patterned semiconductor layer, wherein the gate of the transfer transistor is formed in the second patterned semiconductor layer; and

an interlayer insulating layer interposed between the first patterned semiconductor layer and the second patterned semiconductor layer.

21. The image sensor as set forth in claim 20, further comprising a color filter formed directly on the second patterned semiconductor layer including the photo diode.

22. The mage sensor as set forth in claim 20, further comprising a color filter formed directly on the P-type region enveloping the N-type region.