Semiconductor package including top-surface terminals for mounting another semiconductor package

• US 7,671,457 B1
• Filed: 11/09/2006
• Issued: 03/02/2010
• Est. Priority Date: 05/01/2002
• Status: Expired due to Term

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Rusli, Sukianto, Hiner, David Jon, Huemoeller, Ronald Patrick
• Primary Examiner(s): Parker; Kenneth A
• Assistant Examiner(s): NGUYEN, JOSEPH H
• Application Number:
  US11/595,411
• Time in Patent Office: 1,209 Days
• Field of Search: 257/678, 257/774, 257/777, 257/779, 257/781, 257/686
• US Class Current: 257/678
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H05K 1/056 : the metal substrate being covered by an organic insulating layer
• CPC Class Codes: H05K 2201/09036 : Recesses or grooves in insulating substrate recess in metallic substrate H05K2201/09745
• CPC Class Codes: H05K 2201/09554 : Via connected to metal substrate
• CPC Class Codes: H05K 2203/0723 : Electroplating, e.g. finish plating
• CPC Class Codes: H05K 3/0032 : of organic insulating material
• CPC Class Codes: H05K 3/0035 : of blind holes, i.e. having a metal layer at the bottom
• CPC Class Codes: H05K 3/107 : by filling grooves in the support with conductive material H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence
• CPC Class Codes: H05K 3/1258 : by using a substrate provided with a shape pattern, e.g. grooves, banks, resist pattern
• CPC Class Codes: H05K 3/423 : characterised by electroplating method
• CPC Class Codes: H05K 7/1061 : co-operating by abutting
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49167 : with deforming of conductive path

Abstract

A semiconductor package including top-surface terminals for mounting another semiconductor package provides a three-dimensional circuit configuration that can provide removable connection of existing grid-array packages having a standard design. A semiconductor die is mounted on an electrically connected to a circuit substrate having terminals disposed on a bottom side for connection to an external system. The die and substrate are encapsulated and vias are laser-ablated or otherwise formed through the encapsulation to terminals on the top surface of the substrate that provide a grid array mounting lands to which another grid array semiconductor package may be mounted. The bottom side of the vias may terminate and electrically connect to terminals on the substrate, terminals on the bottom of the semiconductor package (through terminals) or terminals on the top of the semiconductor die. The vias may be plated, paste-filled, filled with a low melting point alloy and may have a conical profile for improved plating performance.

Claims

1. A semiconductor package, comprising:

a semiconductor die;

a substrate including a conductive circuit pattern for connecting electrical connections of the semiconductor die to a plurality of bottom-side terminals accessible from the bottom side of the substrate, wherein the semiconductor die is mounted on a top surface of the substrate;

an encapsulation covering the semiconductor die and at least the top surface of the substrate; and

a plurality of top-surface terminals disposed on a top surface of the encapsulation for mounting and electrically connecting to a second semiconductor package, and wherein the top-surface terminals are electrically connected to at least one of the conductive circuit pattern of the substrate, the electrical connections of the semiconductor die and the bottom-side terminals, wherein the top-surface terminals are provided by conductor-filled vias provided through the encapsulation and substrate and are accessible from the bottom side of the substrate, and wherein at least one of the bottom-side terminals is provided by a bottom side of one of the vias, whereby an electrical interface of the second semiconductor package is accessible from the bottom side of the semiconductor package.

2. The semiconductor package of claim 1, wherein the top-surface terminals are provided by conductor-filled vias provided through the encapsulation and terminating on the conductive pattern of the substrate, whereby an electrical interface of the second semiconductor package is accessible via connection to the circuit pattern of the substrate.

3. The semiconductor package of claim 2, wherein the conductive pattern connects the vias to the bottom-side terminals so that an electrical interface of the second semiconductor package is accessible via connection to the bottom-side terminals.

4. The semiconductor package of claim 2, wherein the conductive pattern connects the vias to the electrical connections of the semiconductor die so that an electrical interface of the second semiconductor package is connected to the semiconductor die.

5. The semiconductor package of claim 1, wherein the top-surface terminals are provided by conductor-filled vias provided through the encapsulation and terminating on the electrical connections of the semiconductor die provided on a top surface of the semiconductor die, whereby an electrical interface of the second semiconductor package is connected to the semiconductor die.

6. The semiconductor package of claim 1, wherein the top-surface terminals form a grid array land configuration for mounting and electrically connecting a grid array semiconductor package as the second semiconductor package.

7. The semiconductor package of claim 1, wherein the top-surface terminals are formed by plated vias extending through the encapsulation to at least one of the conductive circuit pattern of the substrate, the electrical connections of the semiconductor die and the bottom-side terminals, and wherein the vias have a conical cross section, whereby plating uniformity is improved.

8. The semiconductor package of claim 1, wherein the top-surface terminals are formed by vias filled with conductive paste and extending through the encapsulation to provide an interconnect to at least one of the conductive circuit pattern of the substrate, the electrical connections of the semiconductor die and the bottom-side terminals.

9. A semiconductor package, comprising:

a semiconductor die mounted to a substrate, the semiconductor die being electrically connected to a circuit pattern of the substrate, wherein the substrate has a plurality of bottom side electrical terminals on a bottom side;

an encapsulation encapsulating the semiconductor die and at least a top surface of the substrate;

laser-ablated via holes through at least the encapsulation; and

a plurality of top-surface terminals formed by conductor-filled vias within the laser-ablated via holes, the top-surface terminals on a top surface of the semiconductor package for connecting a second semiconductor package to the semiconductor package, wherein the vias extend through the encapsulation and substrate and are accessible from the bottom side of the substrate, and wherein at least one of the bottom side terminals is provided by a bottom side of one of the vias, whereby an electrical interface of the second semiconductor package is accessible from the bottom side of the semiconductor package.

10. The semiconductor package of claim 9, wherein the laser-ablated via holes are formed by a laser.

11. The semiconductor package of claim 9, wherein the vias provide electrical connections from at least one of the plurality of top-surface terminals to the circuit pattern.

12. The semiconductor package of claim 9, wherein the vias provide electrical connections from at least one of the plurality of top-surface terminals to an electrical connection of the semiconductor die.