Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode

• US 7,671,471 B2
• Filed: 02/14/2008
• Issued: 03/02/2010
• Est. Priority Date: 04/20/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Chau, Robert S., Barns, Chris E., Doczy, Mark L., Kavalieros, Jack, Brask, Justin K., Metz, Matthew V., Datta, Suman, Cappellani, Annalisa
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US12/031,409
• Publication Number:
  US 20080135952A1
• Time in Patent Office: 747 Days
• Field of Search: 257/310, 257/750, 257/753, 257/E23.01
• US Class Current: 257/750
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.

Claims

1. A semiconductor device comprising:

a substrate;

a dielectric layer above said substrate, wherein said dielectric layer comprises a trench, and wherein the bottom of said trench has a first portion and a second portion;

a first metal layer, wherein said first metal layer is above said first portion of the bottom of said trench but not above said second portion; and

a second metal layer, wherein said second metal layer is above said second portion of the bottom of said trench and above said first metal layer, and wherein said first metal layer and said second metal layer form a P/N junction at the bottom of said trench, wherein said first metal layer comprises a material that is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide and said second metal layer comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, and a metal carbide.

2. The semiconductor device of claim 1 including a fill metal layer, wherein said fill metal layer is in said trench and above said second metal layer above said first and said second portions of the bottom of said trench, and wherein said fill metal layer comprises a material that is selected from the group consisting of tungsten, aluminum, titanium, and titanium nitride.

3. The semiconductor device of claim 1 wherein the workfunction of said second metal layer and the workfunction of said first metal layer differ by a value in the range of 0.7 eV-1.3 eV.

4. The semiconductor device of claim 1 including a gate dielectric layer, wherein said gate dielectric layer is above said first portion and said second portion of the bottom of said trench and below said first metal layer and said second metal layer.

5. The semiconductor device of claim 4 wherein said gate dielectric layer comprises a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

6. A semiconductor device comprising:

a substrate;

a dielectric layer above said substrate, wherein said dielectric layer comprises a trench, and wherein the bottom of said trench has a first portion and a second portion;

a first metal layer, wherein said first metal layer is above said first portion of the bottom of said trench but not above said second portion; and

a second metal layer, wherein said second metal layer is above said second portion of the bottom of said trench and above said first metal layer, and wherein said first metal layer and said second metal layer form a P/N junction at the bottom of said trench, wherein said second metal layer comprises a material that is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide and said first metal layer comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, and a metal carbide.

7. The semiconductor device of claim 6 including a fill metal layer, wherein said fill metal layer is in said trench and above said second metal layer above said first and said second portions of the bottom of said trench, and wherein said fill metal layer comprises a material that is selected from the group consisting of tungsten, aluminum, titanium, and titanium nitride.

8. The semiconductor device of claim 6 wherein the workfunction of said second metal layer and the workfunction of said first metal layer differ by a value in the range of 0.7 eV-1.3 eV.

9. The semiconductor device of claim 6 including a gate dielectric layer, wherein said gate dielectric layer is above said first portion and said second portion of the bottom of said trench and below said first metal layer and said second metal layer.

10. The semiconductor device of claim 9 wherein said gate dielectric layer comprises a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

11. A semiconductor device comprising:

a substrate;

a dielectric layer above said substrate, wherein said dielectric layer comprises a trench, and wherein the bottom of said trench has a first portion and a second portion;

a first metal layer, wherein said first metal layer is above said first portion of the bottom of said trench but not above said second portion; and

a second metal layer, wherein said second metal layer is above said second portion of the bottom of said trench and above said first metal layer, and wherein said first metal layer and said second metal layer form a P/N junction at the bottom of said trench, at approximately the center of said trench.

12. The semiconductor device of claim 11 wherein the workfunction of said second metal layer and the workfunction of said first metal layer differ by a value in the range of 0.7 eV-1.3 eV.

13. The semiconductor device of claim 11 including a gate dielectric layer, wherein said gate dielectric layer is above said first portion and said second portion of the bottom of said trench and below said first metal layer and said second metal layer.

14. The semiconductor device of claim 13 including a fill metal layer, wherein said fill metal layer is in said trench and above said second metal layer, and wherein said fill metal layer comprises a material that is selected from the group consisting of tungsten, aluminum, titanium, and titanium nitride.

15. The semiconductor device of claim 13 wherein said gate dielectric layer comprises a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

16. The semiconductor device of claim 11 wherein said first metal layer comprises a material that is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide and said second metal layer comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, and a metal carbide.

17. The semiconductor device of claim 11 wherein said second metal layer comprises a material that is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide and said first metal layer comprises a material that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, and a metal carbide.

18. The semiconductor device of claim 11 including a fill metal layer, wherein said fill metal layer is in said trench and above said second metal layer above said first and said second portions of the bottom of said trench, and wherein said fill metal layer comprises a material that is selected from the group consisting of tungsten, aluminum, titanium, and titanium nitride.