Low height vertical sensor packaging

• US 7,671,478 B2
• Filed: 09/02/2005
• Issued: 03/02/2010
• Est. Priority Date: 09/02/2005
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Wathanawasam, Lakshman S., Bratland, Tamara K., Bohlinger, Michael J., Wan, Hong
• Primary Examiner(s): Le; Thao X
• Assistant Examiner(s): ARORA, AJAY
• Application Number:
  US11/219,495
• Publication Number:
  US 20070052077A1
• Time in Patent Office: 1,642 Days
• Field of Search: 257/108, 257/786, 257/E23.151
• US Class Current: 257/786
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/45014 Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01028 Nickel [Ni]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/206 : Length ranges

Abstract

A system and method for packaging a magnetic sensor is described. A sensor die is constructed such that connection pads are situated on two opposing sides of the die in two vertical arrays. Bonding wires connect the connection pads on the sensor die to wire bond pads on a substrate. Alternatively, the connection pads are connected to solderable chip pads on the substrate using flip chip bonding. Traces and vias are used to connect the wire bond pads or the solderable chip pads to sensor package pads. The sensor package pads are located on a single side of a sensor package for mounting on a next assembly. The next assembly has a land pattern that includes at least one leveling pad for positioning the sensor die perpendicular to the next assembly while being mounted and a single row of pads for making connections to the sensor package.

Claims

1. A circuit package for minimizing height, comprising in combination:

a die having a plurality of connection pads, wherein all of the connection pads are arranged to form a first vertical array and a second vertical array;

wherein the first vertical array comprises at least a first bottom connection pad and a first top connection pad;

wherein the second vertical array comprises at least a second bottom connection pad and a second top connection pad; and

wherein the first vertical array of connection pads is located on an opposing side of the die from the second vertical array of connection pads; and

a substrate, wherein the die is mounted on the substrate so that the first and second vertical arrays of connection pads are positioned to be substantially parallel to a side of the substrate that defines a height of the circuit package with respect to a mounting surface of the circuit package;

wherein the first vertical array and the second vertical array define a vertical region with respect to the substrate, wherein the vertical region is an area on the substrate between a lower boundary bounded by a line that is substantially perpendicular to the first and second vertical arrays and passes through a bottom of the lowest of either the first bottom connection pad and the second bottom connection pad and with an upper boundary bounded by a line that is substantially perpendicular to the first and second vertical arrays and passes through a top of the highest of either the first top connection pad and the second top connection pad; and

wherein the connection pads are electrically connected to a plurality of wire bond pads all of which are located on the substrate within the vertical region, wherein the wire bond pads are electrically connected to circuit package pads all of which are located on a single side of the circuit package.

2. The circuit package of claim 1, wherein the die is a magnetic sensor die.

3. The circuit package of claim 1, wherein the connection pads are confined within an active region of the die.

4. The circuit package of claim 1, wherein the first and second vertical arrays of connection pads are connected to wire bond pads on the substrate with bonding wire.

5. The circuit package of claim 4, wherein the wire bond pads are arranged to form two vertical arrays, wherein a first vertical array of wire bond pads is located on a portion of the substrate adjacent to a side of the die containing the first vertical array of connection pads, and wherein a second vertical array of wire bond pads is located on a portion of the substrate adjacent to a side of the die containing the second vertical array of connection pads.

6. The circuit package of claim 5, wherein the first vertical array of wire bond pads is located on the substrate to be substantially parallel with the first vertical array of connection pads, and wherein the second vertical array of wire bond pads is located on the substrate to be substantially parallel with the second vertical array of connection pads.

7. The circuit package of claim 4, wherein the wire bond pads are connected by traces to vias.

8. The circuit package of claim 7, wherein the vias are connected by traces to circuit package pads.

9. The circuit package of claim 1, wherein the first and second vertical arrays of connection pads are connected to solderable chip pads on the substrate using flip chip bonding.

10. The circuit package of claim 9, wherein the solderable chip pads are connected by traces to vias.

11. The circuit package of claim 10, wherein the vias are connected by traces to circuit package pads.

12. The circuit package of claim 11, wherein the circuit package pads are located on a single side of the circuit package.

13. A land pattern located on an assembly to which a circuit package is to be mounted, comprising in combination:

at least one leveling pad at a first side of a substrate for positioning the circuit package perpendicular with respect to the assembly;

wherein the circuit package comprises a sensor die mounted on a substrate and encapsulated by a mold; and

wherein the sensor die has a plurality of connection pads, wherein all of the connection pads are arranged to form a first vertical array and a second vertical array;

wherein the first vertical array comprises at least a first bottom connection pad and a first top connection pad;

wherein the second vertical array comprises at least a second bottom connection pad and a second top connection pad; and

wherein the first vertical array of connection pads is located on an opposing side of the die from the second vertical array of connection pads; and

wherein the sensor die is mounted on the substrate so that the first and second vertical arrays of connection pads are positioned to be substantially parallel to a side of the substrate that defines a height of the circuit package with respect to a mounting surface of the circuit package;

wherein the first vertical array and the second vertical array define a vertical region with respect to the substrate, wherein the vertical region is an area on the substrate between a lower boundary bounded by a line that is substantially perpendicular to the first and second vertical arrays and passes through a bottom of the lowest of either the first bottom connection pad and the second bottom connection pad and with an upper boundary bounded by a line that is substantially perpendicular to the first and second vertical arrays and passes through a top of the highest of either the first top connection pad and the second top connection pad; and

wherein the connection pads are electrically connected to a plurality of wire bond pads all of which are located on the substrate within the vertical region, wherein the wire bond pads are electrically connected to circuit package pads all of which are located on a single side of the circuit package; and

a single row of pads at a second side of the substrate opposite the first side of the substrate for making connections to one side of the circuit package.