Method and apparatus for selectively maintaining circuit power when higher voltages are present

• US 7,671,489 B1
• Filed: 01/17/2002
• Issued: 03/02/2010
• Est. Priority Date: 01/26/2001
• Status: Expired due to Fees

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: SIRF Technology Incorporated (Qualcomm, Inc.)
• Inventors: Uy, Allan Paul T., McConnell, Richard Joseph
• Primary Examiner(s): Paladini; Albert W
• Assistant Examiner(s): KAPLAN, HAL IRA
• Application Number:
  US10/051,726
• Time in Patent Office: 2,966 Days
• Field of Search: 307/87, 307/130, 307/65, 307/85, 307/86, 327/518, 327/520
• US Class Current: 307/86
• CPC Class Codes: H02J 9/061 for DC powered loads

Abstract

A method and apparatus for detecting the presence of a specified voltage source and automatically switching off a second voltage source regardless of voltage source potential of the two voltage sources are disclosed. The present invention uses pinch-off of a JFET, controlled by an inverter, to control a backup power supply based on the availability of the main supply.

Claims

1. An apparatus for selectively providing power from a secondary power source, comprising:

a field effect transistor, having a source coupled to the secondary power source;

a first diode, coupled to a drain of the field effect transistor and to a device to be powered;

a second diode, coupled to the primary power source and the device to be powered; and

an inverter, coupled to the primary power source and to a gate of the field effect transistor, wherein the inverter maintains the field effect transistor in a pinched-off condition and prevents a current flow from the secondary power source whenever the primary power source is available.

2. The apparatus of claim 1, wherein the field effect transistor is a depletion mode field effect transistor.

3. The apparatus of claim 2, wherein the depletion mode field effect transistor is an n-channel depletion mode field effect transistor.

4. The apparatus of claim 1, wherein the field effect transistor is an enhancement mode field effect transistor.

5. The apparatus of claim 4, wherein the enhancement mode transistor is a p-channel enhancement mode field effect transistor.

11. The apparatus of claim 1, further including a reset integrated circuit (“

IC”

) coupled to the inverter.

6. An apparatus for selectively providing power from a secondary power source, comprising:

a first diode, coupled between the primary power source and a device to be powered;

a second diode, coupled to the secondary power source;

a field effect transistor, having a source coupled to the second diode and a drain coupled to the first diode and the device to be powered; and

an inverter, coupled to the primary power source and to a gate of the field effect transistor, wherein the inverter maintains the field effect transistor in a pinched-off condition and prevents a current flow from the secondary power source whenever the primary power source is available.

7. The apparatus of claim 6, wherein the field effect transistor is a depletion mode field effect transistor.

8. The apparatus of claim 7, wherein the depletion mode field effect transistor is an n-channel depletion mode field effect transistor.

9. The apparatus of claim 6, wherein the field effect transistor is an enhancement mode field effect transistor.

10. The apparatus of claim 9, wherein the enhancement mode transistor is a p-channel enhancement mode field effect transistor.

12. The apparatus of claim 6, further including a reset IC coupled to the inverter.