Semiconductor device having an integrated, self-regulated PWM current and power limiter and method

• US 7,671,571 B2
• Filed: 02/20/2008
• Issued: 03/02/2010
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Burlak, Gary J., Mirowski, Marian
• Primary Examiner(s): Patel; Rajnikant B
• Application Number:
  US12/070,710
• Publication Number:
  US 20080284404A1
• Time in Patent Office: 741 Days
• Field of Search: 307 38- 41, 361 23- 33, 361/91.1, 290448-450, 290/464, 290/490, 290/497, 290501-506, 320/128, 320/150, 323272-276, 323/280, 323/907, 323/908
• US Class Current: 323/275
• CPC Class Codes: H02J 1/00 Circuit arrangements for dc mains or dc distribution networks
• CPC Class Codes: H02M 1/0012 Control circuits using digital or numerical techniques in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 17/18 Modifications for indicating state of switch
• CPC Class Codes: H03K 2017/0806 against excessive temperature

Abstract

A method includes receiving an activation signal at a semiconductor device and generating an output power signal at the semiconductor device in response to receiving the activation signal. The output power signal has a duty cycle. The method also includes providing the output power signal to a load. The output power signal provides power to the load. An amount of power provided to the load is based on the duty cycle of the output power signal. In addition, the method includes adjusting the duty cycle of the output power signal using at least one of a current limiter and a power limiter integrated in the semiconductor device.

Claims

1. A method, comprising:

receiving an external activation signal at a semiconductor device;

generating an output power signal at the semiconductor device in response to receiving the activation signal, the output power signal having a duty cycle;

providing the output power signal to an external load, the output power signal providing power to the load, an amount of power provided to the load based on the duty cycle of the output power signal; and

detecting a problem in the semiconductor device based on a measurement of temperature in the semiconductor device; and

in response to detecting the problem, placing the semiconductor device in a self-limiting mode in which at least one of a reduced amount of current and a reduced amount of power is provided to the load.

2. The method of claim 1, wherein placing the semiconductor device in a self-limiting mode further comprises:

adjusting the duty cycle of the output power signal using at least one of a current limiter and a power limiter integrated in the semiconductor device.

3. The method of claim 1, wherein detecting a problem in the semiconductor device based on measuring temperature in the semiconductor device comprises:

measuring one or more temperatures within the semiconductor device; and

comparing at least one of (1) the one or more measured temperatures and (ii) one or more calculated temperature rise times and gradients to one or more thresholds.

4. The method of claim 1, wherein placing the semiconductor device in the self-limiting mode reduces thermal stresses in the semiconductor device.

5. The method of claim 1, wherein placing the semiconductor device in the self-limiting mode controls temperature of the semiconductor device to avoid thermal shutdown.

6. The method of claim 1, further comprising:

storing information identifying the detected problem in a fault storage buffer.

7. The method of claim 1, wherein generating the output power signal comprises driving a transistor coupled between a power supply and the load into conducting and non-conducting states to produce the output power signal.

8. The method of claim 1, wherein the semiconductor device performs the receiving, generating, providing, detecting and placing steps in a stand-alone mode without any external controller.

9. The method of claim 1, wherein the load comprises one or more of:

a motor, a solenoid, and a lamp in a vehicle.

10. A semiconductor device for use with an external power supply, an external load and an external activation signal, the semiconductor device comprising:

an output power signal generator capable of generating an output power signal, the output power signal having a duty cycle and providing power to the load, an amount of power provided to the load based on the duty cycle of the output power signal;

a temperature sensor for measuring temperature within the semiconductor device;

a controller capable of causing the output power signal generator to generate the output power signal in response to receiving the activation signal and placing the semiconductor device in a self-limiting mode in which at least one of a reduced amount of current or a reduced amount of power is provided to the load when a measured temperature exceeds a threshold.

11. The semiconductor device of claim 10, wherein the controller is capable of adjusting the duty cycle of the output power signal to reduce thermal stresses in the semiconductor device.

12. The semiconductor device of claim 10, wherein the controller is capable of adjusting the duty cycle of the output power signal to control temperature of the semiconductor device to avoid thermal shutdown.

13. The semiconductor device of claim 10, wherein the output power signal generator comprises a switching transistor coupled between the power supply and the load;

and

further comprising a driver capable of driving the transistor into conducting and non-conducting states to produce the output power signal, the driver capable of being controlled by the controller.

14. The semiconductor device of claim 10, further comprising:

a fault storage buffer capable of storing a fault condition identifying a temperature problem in the semiconductor device.

15. The semiconductor device of claim 10, wherein the controller is capable of adjusting the duty cycle of the output power signal when a measured temperature gradient exceeds a threshold.

16. A system, comprising:

a power supply capable of providing a supply voltage; and

a semiconductor device capable of;

generating an output power signal using the supply voltage in response to receipt of an external activation signal, the output power signal having a duty cycle;

providing the output power signal to an external load, an amount of power provided to the load based on the duty cycle of the output power signal;

detecting a problem in the semiconductor device based on a measurement of temperature in the semiconductor device; and

in response to detecting the problem, placing the semiconductor device in a self-limiting mode in which at least one of a reduced amount of current and a reduced amount of power is provided to the load.

17. The system of claim 16, further comprising:

a controller is capable of adjusting the duty cycle of the output power signal to reduce thermal stresses in the semiconductor device.

18. The system of claim 16, further comprising:

a controller is capable of adjusting the duty cycle of the output power signal to control temperature of the semiconductor device to avoid thermal shutdown.

19. The system of claim 16, further comprising:

a controller; and

an output power signal generator including a switching transistor coupled between the power supply and the load and a driver capable of driving the transistor into conducting and non-conducting states to produce the output power signal, the driver capable of being controlled by the controller.

20. The system of claim 16, further comprising:

a fault storage buffer capable of storing a fault condition identifying a temperature problem in the semiconductor device.