Method and apparatus for quantifying and minimizing skew between signals
First Claim
1. A signal delay measurement circuit, comprising:
- an input register defined to receive a test data signal and output the test data signal in accordance with a test clock signal;
an output register defined to receive a delayed version of the test data signal and output the delayed version of the test data signal in accordance with a delayed version of the test clock signal;
an emulation module connected between the input register and the output register, the emulation module defined to emulate an actual signal transmission path for which signal delay is to be measured, the emulation module defined to introduce signal delay in the test data signal as the test data signal is transmitted from the input register to arrive at the output register as the delayed version of the test data signal; and
a delay chain defined to introduce a controllable amount of signal delay in the test clock signal to generate the delayed version of the test clock signal, wherein a measured delay of the emulated signal path is calculated from the delayed version of the test clock signal when the delayed version of the test data signal is clocked through the output register.
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Abstract
Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.
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Citations
20 Claims
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1. A signal delay measurement circuit, comprising:
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an input register defined to receive a test data signal and output the test data signal in accordance with a test clock signal; an output register defined to receive a delayed version of the test data signal and output the delayed version of the test data signal in accordance with a delayed version of the test clock signal; an emulation module connected between the input register and the output register, the emulation module defined to emulate an actual signal transmission path for which signal delay is to be measured, the emulation module defined to introduce signal delay in the test data signal as the test data signal is transmitted from the input register to arrive at the output register as the delayed version of the test data signal; and a delay chain defined to introduce a controllable amount of signal delay in the test clock signal to generate the delayed version of the test clock signal, wherein a measured delay of the emulated signal path is calculated from the delayed version of the test clock signal when the delayed version of the test data signal is clocked through the output register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A delay element calibration circuit, comprising:
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an input register defined to receive a test data signal and output the test data signal in accordance with a test clock signal, wherein a period of the test clock signal is adjustable; an output register defined to receive a delayed version of the test data signal and output the delayed version of the test data signal in accordance with the test clock signal, the output register is directly coupled to the test clock signal; and a chain of delay elements connected between an output of the input register and an input of the output register, the chain of delay elements defined to introduce signal delay in the test data signal as the test data signal is transmitted from the input register to arrive at the output register as the delayed version of the test data signal. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method of measuring a signal delay, comprising:
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receiving a test data signal and a test clock signal at an input register; emulating a signal delay of an actual signal transmission path to be measured using an emulation module; and adjusting a signal delay in the test clock signal using a delay chain, wherein the signal delay of the emulated actual signal transmission path is calculated from the signal delay in the test clock signal when the delayed version of the test data signal from the input register is clocked through an output register. - View Dependent Claims (18, 19, 20)
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Specification