Single-supply, single-ended level conversion circuit for an integrated circuit having multiple power supply domains

• US 7,671,629 B2
• Filed: 04/08/2008
• Issued: 03/02/2010
• Est. Priority Date: 04/08/2008
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Kenkare, Prashant U., Zhang, Shayan, Delk, Karen
• Primary Examiner(s): Cho, James H.
• Assistant Examiner(s): Tran, Jany
• Application Number:
  US12/099,485
• Publication Number:
  US 20090251173A1
• Time in Patent Office: 693 Days
• Field of Search: 326/62, 326/63, 326/68, 326 80- 83, 326/86, 326/87, 327199-204, 327/333
• US Class Current: 326/81
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A circuit comprises first, second, third, and fourth transistors. The first transistor has a first current electrode, a control electrode for receiving an input signal, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor for providing an output signal, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to a first power supply voltage terminal. The third transistor has a first current electrode coupled to a second power supply voltage terminal, a control electrode, and a second current electrode coupled to the first current electrode of the first transistor. The fourth transistor has a first current electrode coupled to the control electrode of the third transistor, a control electrode coupled to the control electrodes of the first and second transistors, and a second current electrode coupled to the control electrode of the first transistor.

Claims

1. A circuit comprising:

a first transistor having a first current electrode, a control electrode for receiving an input signal, and a second current electrode;

a second transistor having a first current electrode coupled to the second current electrode of the first transistor for providing an output signal, a control electrode coupled to the control electrode of the first transistor for receiving the input signal, and a second current electrode coupled to a first power supply voltage terminal;

an inverter having an input coupled to the second current electrode of the first transistor, and an output; and

a leakage reduction circuit comprising;

a third transistor having a first current electrode coupled to a second power supply voltage terminal, a control electrode coupled to the output of the inverter, and a second current electrode coupled to the first current electrode of the first transistor; and

a fourth transistor having a first current electrode coupled to the control electrode of the third transistor, a control electrode coupled to the control electrodes of the first and second transistors, and a second current electrode coupled to the control electrode of the first transistor.

2. The circuit of claim 1, wherein the first, third, and fourth transistors are P-channel transistors and the second transistor is an N-channel transistor.

3. The circuit of claim 1, wherein the first power supply voltage terminal is coupled to ground and the second power supply voltage terminal is for receiving a first power supply voltage, wherein the input signal is provided from a circuit that is supplied with a second power supply voltage, the second power supply voltage being different than the first power supply voltage.

4. The circuit of claim 1, wherein the circuit is tristateable.

5. The circuit of claim 4, further comprising a fifth transistor and a sixth transistor coupled in series between the first and second transistors, a control electrode of each of the fifth and sixth transistors for receiving a control signal.

6. The circuit of claim 1, wherein the circuit is implemented as a portion of a master-slave flip-flop.

7. The circuit of claim 6, wherein the master-slave flip-flop further comprises a test input for receiving a test signal.

8. The circuit of claim 1, wherein the circuit is implemented on an integrated circuit, the integrated circuit comprising a first domain powered by a first power supply voltage and a second domain powered by a second power supply voltage, wherein the first power supply voltage is different than the second power supply voltage.

9. The circuit of claim 8, wherein the input signal originates in the first domain and the output signal is provided to the second domain.

10. A circuit comprising:

a first transistor having a first current electrode, a control electrode for receiving an input signal, and a second current electrode;

a second transistor having a first current electrode coupled to the second current electrode of the first transistor for providing an output signal, a control electrode coupled to the control electrode of the first transistor for receiving the input signal, and a second current electrode coupled to a first power supply voltage terminal; and

a leakage reduction circuit comprising;

a third transistor having a first current electrode coupled to a second power supply voltage terminal, a control electrode, and a second current electrode coupled to the first current electrode of the first transistor;

a fourth transistor having a first current electrode coupled to the control electrode of the third transistor, a control electrode coupled to the control electrodes of the first and second transistors, and a second current electrode coupled to the control electrode of the first transistor; and

a fifth transistor having a first current electrode coupled to the second power supply voltage terminal, a control electrode connected to the control electrode of the first, second, and fourth transistors, and a second current electrode coupled to the first current electrode of the fourth transistor.

11. The circuit of claim 10, wherein the first, third, and fourth transistors are P-channel transistors and the second and fifth transistors are N-channel transistors.

12. The circuit of claim 10, further comprising a sixth transistor and a seventh transistor coupled in series between the first and second transistors, a control electrode of each of the sixth and seventh transistors for receiving a control signal.

13. The circuit of claim 10, wherein the circuit is implemented as a portion of a master-slave flip-flop.

14. The circuit of claim 10, wherein the circuit is implemented on an integrated circuit, the integrated circuit comprising a first domain powered by a first power supply voltage and a second domain powered by a second power supply voltage, wherein the first power supply voltage is different than the second power supply voltage, and wherein the input signal is provided from the first domain and the circuit is powered by the second power supply voltage.

15. A circuit comprising:

a first transistor having a first current electrode, a control electrode for receiving an input signal, and a second current electrode, wherein the input signal originates from a portion of an integrated circuit powered by a first power supply voltage;

a second transistor having a first current electrode coupled to the second current electrode of the first transistor for providing an output signal, a control electrode coupled to the control electrode of the first transistor for receiving the input signal, and a second current electrode coupled to a ground terminal; and

a leakage reduction circuit comprising;

a third transistor having a first current electrode coupled to a second power supply voltage terminal, a control electrode, and a second current electrode coupled to the first current electrode of the first transistor, wherein the second power supply voltage terminal is for receiving a second power supply voltage different from the first power supply voltage;

a fourth transistor having a first current electrode coupled to the control electrode of the third transistor, a control electrode coupled to the control electrodes of the first and second transistors, and a second current electrode coupled to the control electrode of the first transistor; and

a fifth transistor having a first current electrode coupled to the second power supply voltage terminal, a control electrode connected to the control electrode of the first, second, and fourth transistors, and a second current electrode coupled to the first current electrode of the fourth transistor.

16. The circuit of claim 15, wherein the first, third, and fourth transistors are P-channel transistors and the second and fifth transistors are N-channel transistors.