Memory cell with built-in process variation tolerance
First Claim
1. A semiconductor memory cell with built-in process variation tolerance, comprising:
- a pair of cross-coupled inverters each having first and second series-connected transistors and each having a switching threshold;
an access transistor electrically connected to a first of said inverters; and
a feedback mechanism for changing the switching threshold of at least said first inverter in response to an input transition.
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Abstract
A Schmitt Trigger (ST) based, fully differential, 10-transistor (10T) SRAM (Static Random Access Memory) bitcell suitable for sub-threshold operation. The Schmitt trigger based bitcell achieves 1.56× higher read static noise margin (SNM) (VDD=400 mV) compared to a conventional 6T cell. The robust Schmitt trigger based memory cell exhibits built-in process variation tolerance that gives tight SNM distribution across the process corners. It utilizes fully differential operation and hence does not require any architectural changes from the present 6T architecture. The 10T bitcell has two cross-coupled Schmitt trigger inverters which each consist of four transistors, including a PMOS transistor and two NMOS transistors in series, and an NMOS feedback transistor which is connected between the inverter output and the junction between the series-connected NMOS transistors. Each inverter has one associated NMOS access transistor.
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Citations
8 Claims
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1. A semiconductor memory cell with built-in process variation tolerance, comprising:
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a pair of cross-coupled inverters each having first and second series-connected transistors and each having a switching threshold; an access transistor electrically connected to a first of said inverters; and a feedback mechanism for changing the switching threshold of at least said first inverter in response to an input transition. - View Dependent Claims (2, 3, 4, 5)
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6. An SRAM bitcell with built-in process variation tolerance, comprising:
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a pair of cross-coupled Schmitt trigger inverters, each including a PMOS transistor in series with two series-connected NMOS transistors; a memory cell access transistor electrically connected to each of said Schmitt trigger inverters; a first bit line connected to one of said Schmitt trigger inverters through a first of said access transistors; a second bit line connected to the other of said Schmitt trigger inverters through a second of said access transistors; and a word line connected to control inputs for both access transistors. - View Dependent Claims (7, 8)
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Specification