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Memory cell with built-in process variation tolerance

  • US 7,672,152 B1
  • Filed: 02/27/2008
  • Issued: 03/02/2010
  • Est. Priority Date: 02/27/2007
  • Status: Active Grant
First Claim
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1. A semiconductor memory cell with built-in process variation tolerance, comprising:

  • a pair of cross-coupled inverters each having first and second series-connected transistors and each having a switching threshold;

    an access transistor electrically connected to a first of said inverters; and

    a feedback mechanism for changing the switching threshold of at least said first inverter in response to an input transition.

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