Method of and system for determining the delay of digital signals

• US 7,672,363 B2
• Filed: 05/27/2005
• Issued: 03/02/2010
• Est. Priority Date: 05/27/2004
• Status: Active Grant

• Current Assignee: Tag Safety Systems Incorporated
• Original Assignee: Tag Safety Systems Incorporated
• Inventors: Bokhour, Edward
• Primary Examiner(s): DEPPE, BETSY LEE
• Application Number:
  US11/139,063
• Publication Number:
  US 20050276318A1
• Time in Patent Office: 1,740 Days
• Field of Search: 375/219, 375/220, 375/295, 375/358, 375/363, 375/221, 375/354, 375/355, 375/356, 375/257, 375/259, 375/377, 375/224, 455/24, 455/69, 455/73, 455/456.1, 342/118, 342/126, 342/357.08, 342/450, 342/458, 702/176
• US Class Current: 375/221
• CPC Class Codes: G01S 13/76 wherein pulse-type signals are transmitted
• CPC Class Codes: G01S 13/878 Combination of several spaced transmitters or receivers of known location for determining the position of a transponder or a reflector G01S13/874 takes precedence
• CPC Class Codes: H04J 3/0682 by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging

Abstract

A method of and system for determining the time required for a digital bit or bit stream to traverse a round-trip path from a source transceiver to at least one destination transceiver and back is disclosed. The relative timing of the transmitted bit or bit stream is compared to the return bit or bit stream using a high speed comparison configuration so as to provide in substantially real-time various measurements related to or derived from the time required to traverse the round trip path, including distance measurement in indoor positioning, real-time locating, adaptive cruise control, intelligent transportation systems, robotics, collision avoidance, personnel accountability, emergency location, search/rescue. In addition, a method of and system for determining the distance between transceivers, and a method of and system for determining the angular position of a transceiver with respect to at least two other transceivers are disclosed.

Claims

1. A method of determining a measurement of the time required for a digital bit or a bit stream including a plurality of bits to traverse a round-trip path from a source transceiver to at least one destination transceiver and back, the method comprising:

comparing the relative timing between (a) one or more transmitted bits transmitted from the source transceiver to one destination transceiver and (b) corresponding one or more return bits transmitted from the destination transceiver back to the source transceiver, wherein the step of comparing includes using a high speed comparison configuration so as to provide in substantially real-time one or more measurements related to or derived from a measurement of the time required by each of said one or more transmitted bits and the corresponding one or more return bits to traverse a respective portion of the round trip path.

2. A method according to claim 1, wherein comparing the relative timing includes using the high speed comparison configuration located at the source transceiver, or at both the source and destination transceivers.

3. A method according to claim 1, further including transmitting the one or more transmitted bits at a clock rate, and sampling the one or more transmitted bits and the corresponding one or more return bits at a multiple of the clock rate prior to comparing the relative timing of the one or more transmitted bits and the corresponding one or more return bits.

4. A method according to claim 1, further including determining a measurement of the distance between the source transceiver and the destination transceiver as a function of the time required to traverse the round trip path.

5. A method according to claim 1, further including determining the two dimensional azimuth angle between the source transceiver and two other transceivers including the destination transceiver.

6. A method of determining a measurement of the time required for a digital bit or bit stream to traverse a round-trip path from a source transceiver to at least one destination transceiver and back, the method comprising:

comparing the relative timing between (a) a transmitted bit or bit stream transmitted from the source transceiver to one destination transceiver and (b) a return bit or bit stream transmitted from the destination transceiver back to the source transceiver, wherein the step of comparing includes using a high speed comparison configuration so as to provide in substantially real-time one or more measurements related to or derived from a measurement of the time required by the transmitted bit or bit stream and the return bit or bit stream to traverse the round trip path;

wherein comparing the relative timing includes measuring errors in such comparison in substantially real-time, and correcting for such errors.

7. A method according to claim 6, wherein the errors are one or more of the following:

fixed delays and jitter.

8. A method of obtaining a measurement of a time delay between (a) the transmission at a clock rate of a transmitted digital signal by a first transceiver to a second transceiver and (b) the reception of a return digital signal transmitted by the second transceiver to the first transceiver in response to receiving the transmitted digital signal, the method comprising:

oversampling the return digital signal at an oversampling rate S so as to provide an oversampled return digital signal, wherein the oversampling rate S is a multiple of the sampling clock rate of the transmitted digital signal;

comparing the transmitted digital signal to the oversampled return digital signal and generating at least two bytes of bits at the oversampled rate wherein each byte has a leading and a trailing edge, one of the bytes corresponding to a differential time period measurement during which the leading edge of the transmitted digital signal is transmitted and the leading edge of the return digital signal is received by the first transceiver, and the other of the bytes corresponding to a differential time period measurement during which the trailing edge of the transmitted digital signal is transmitted and the trailing edge of the returned digital signal is received by the first transceiver;

assigning a value to each of the bytes as a function of the ordering of the bits within each of the bytes so as to include a least significant bit and a most significant bit, wherein the sequence of the least significant bit to most significant bit of one byte is temporally reversed for the second byte; and

determining the time delay as a function of the assigned values of the two bytes.

9. The method according to claim 8, further including:

compensating for noise in the return digital signal.

10. The method according to claim 9, wherein the step of compensating for noise in the return digital signal includes compensating for an out-of-phase component of the noise.

11. The method according to claim 10, wherein the step of compensating for the out-of phase component of noise includes:

determining the out-of phase component as a function of the difference between the logical inverse of one of the bytes and the logical value of the other of the bytes.

12. A system for making a measurement of the amount of time required for at least one digital bit to traverse a round-trip path from a source transceiver to at least one destination transceiver and back, the system comprising:

a high speed comparison configuration configured and arranged so as to (a) determine a measurement of the relative timing between a transmitted bit produced at a clock rate by the source transceiver and transmitted to a destination transceiver, and a corresponding return bit produced by the destination transceiver in response to receiving a respective transmitted bit from the source transceiver and received by the source transceiver; and

(b) provide in substantially real-time at least one measurement related to or derived from a measurement of the time required for the transmitted bit and the corresponding return bit to traverse the round trip path.

13. A system according to claim 12, wherein the high speed comparison configuration is located at the source transceiver, or at both the source and destination transceivers.

14. A system according to claim 12, further including a sampling configuration configured so as to sample each transmitted bit and the corresponding return bit at a multiple of the clock rate of the transmitted bit prior to comparing the relative timing between each transmitted bit and its corresponding return bit.

15. A system according to claim 12, further including a processor configured and arranged so as to determine the distance between the source transceiver and the destination transceiver as a function of the time required to traverse the round trip path.

16. A system according to claim 12, further including a processor configured and arranged so as to determine the two dimensional azimuth angle position of the source transceiver with respect to the destination transceiver and one other transceiver.

17. A system for making a measurement of the amount of time required for a digital bit or bit stream to traverse a round-trip path from a source transceiver to at least one destination transceiver and back, the system comprising:

a high speed comparison configuration configured and arranged so as to (a) determine a measurement of the relative timing between a transmitted bit or bit stream produced at a clock rate by the source transceiver and transmitted to a destination transceiver, and a return bit or bit stream produced by the destination transceiver in response to receiving the transmitted bit or bit stream from the source transceiver and received by the source transceiver;

(b) provide in substantially real-time at least one measurement related to or derived from a measurement of the time required to traverse the round trip path, wherein the high speed comparison configuration includes an error correction circuit configured and arranged so as to measure and correct for errors.

18. A system according to claim 17, wherein the error correction circuit is configured and arranged so as to correct for one or more of the following:

fixed delays and jitter.

19. A system for determining the distance between two transceivers in substantially real time using a measurement of the delay between (a) transmission at a clock rate of a transmitted digital signal by one of the transceivers functioning as a source transceiver and the other of the transceivers functioning as a destination transceiver and (b) reception of a return digital signal transmitted by the destination transceiver to the source transceiver in response to receiving the transmitted digital signal, the system comprising:

the source and destination transceivers configured and arranged so as to define at least in part a round trip transmission path of the transmitted digital signal and the return digital signal;

the source transceiver including an oversampling component configured and arranged so as to oversample the return digital signal at an oversampling rate S so as to provide an oversampled return signal, wherein the oversampling rate S is a multiple of the clock rate of the transmitted digital signal;

a high speed comparison configuration configured and arranged so as to compare the transmitted digital signal to the oversampled return digital signal and generating at least two bytes of bits at the oversampling rate, wherein one of the bytes corresponds to a measurement of a differential time period during which a leading edge of the transmitted digital signal is transmitted and a leading edge of the return digital signal is received by the source transceiver, and the other of the bytes corresponds to a measurement of the differential time period during which a trailing edge of the transmitted digital signal is transmitted and a trailing edge of the returned signal is received by the source transceiver;

a value assignment component configured and arranged so as to assign a value to each of the bytes as a function of an ordering of the bits of each of the bytes, wherein the sequence of the least significant bit to most significant bit of one byte is temporally reversed; and

a delay determination component configured and arranged so as to determine the delay as a function of the assigned values of the two bytes.

20. The system according to claim 19, further including a processor configured and arranged so as to accumulate a plurality of assigned values representing the delays for a plurality of transmitted and returned bits.

21. The system according to claim 20, further including a noise compensation component configured and arranged so as to compensate for noise in the return digital signal.

22. The system according to claim 21, wherein the noise compensation component is configured and arranged so as to compensate for an out-of-phase component of the noise.

23. The system according to claim 22, wherein the noise compensation component is configured and arranged so as to determine the out-of-phase component of noise as a function of the difference between a logical inverse of one of the bytes to a logical value of the other of the bytes.

24. The system according to claim 19, further including a noise compensation component configured and arranged so as to compensate for noise in the return digital signal.

25. The system according to claim 24, wherein the noise compensation component is configured and arranged so as to compensate for an out-of-phase component of the noise.

26. The system according to claim 25, wherein the noise compensation component is configured and arranged so as to determine an out-of-phase component as a function of the difference between a logical inverse of one of the bytes to a logical value of the other of the bytes.