Radio receiver, system on a chip integrated circuit and methods for use therewith

• US 7,672,403 B2
• Filed: 11/22/2005
• Issued: 03/02/2010
• Est. Priority Date: 11/22/2005
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: SigmaTel Incorporated (NXP Semiconductors NV)
• Inventors: Lowe, Erich, May, Michael R.
• Primary Examiner(s): Wang, Ted M
• Application Number:
  US11/287,570
• Publication Number:
  US 20070116150A1
• Time in Patent Office: 1,561 Days
• Field of Search: 375/316, 375/136, 375/147, 375/326, 375/354
• US Class Current: 375/316
• CPC Class Codes: H03D 3/007 by converting the oscillations into two quadrature related signals H03D3/245 takes precedence
• CPC Class Codes: H03J 1/0008 using a central processing unit, e.g. a microprocessor digital tuning in general H03J5/0245

Abstract

A system on a chip integrated circuit includes a first in-phase digital submodule and a first quadrature phase digital submodule such that the first in-phase digital submodule and the first quadrature phase digital submodule are operable to produce at least one output signal based on at least one input signal. A digital clock generator generates a first in-phase digital clock signal having a plurality of first in-phase digital clock cycles over a predetermined period and a first quadrature phase digital clock signal having a plurality of first quadrature phase digital clock cycles over the predetermined period. The plurality of first in-phase digital clock cycles are substantially interleaved with the plurality of first quadrature phase digital clock cycles over the predetermined period.

Claims

1. A radio receiver comprising:

an analog front end for receiving a received radio signal containing a selected one of a plurality of channel signals, and for converting the selected one of the plurality of channel signals into a digital signal that includes an in-phase signal and a quadrature phase signal;

a digital section, operably coupled to the analog front end, for converting the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channel signals, the digital section having a first in-phase digital submodule and a first quadrature phase digital submodule; and

a digital clock generator, operably coupled to the first in-phase digital submodule and the first quadrature phase digital submodule, for generating a first in-phase digital clock signal having a plurality of first in-phase digital clock cycles over a predetermined period and a first quadrature phase digital clock signal having a plurality of first quadrature phase digital clock cycles over the predetermined period, wherein the plurality of first in-phase digital clock cycles are substantially interleaved with the plurality of first quadrature phase digital clock cycles over the predetermined period, wherein the digital clock generator generates a base clock signal at a base clock frequency that varies based on the selected one of the plurality of channel signals, wherein the plurality of first in-phase digital clock cycles and the plurality of first quadrature phase digital clock cycles are substantially constant over the predetermined period, wherein the base clock frequency is less than a carrier frequency of the selected one of the plurality of channel signals, and wherein the base clock frequency and integer multiples of the base clock frequency are not equal to the carrier frequency of the selected one of the plurality of channel signals.

2. The radio receiver of claim 1 wherein the plurality of first in-phase digital clock cycles are equal to the plurality of first quadrature phase digital clock cycles over the predetermined period.

3. The radio receiver of claim 1 wherein the digital clock generator substantially alternates between generating one or more of the plurality of first in-phase digital clock cycles with one or more of the plurality of first quadrature phase digital clock cycles over the predetermined period.

4. The radio receiver of claim 1 wherein the digital clock generator generates at least one of the plurality of first in-phase digital clock cycles in synchronism with at least one of the plurality of first quadrature phase digital clock cycles over the predetermined period.

5. The radio receiver of claim 1 wherein the received radio signal is one of:

a broadcast frequency modulated radio signal, a broadcast amplitude modulated radio signal, a broadcast satellite radio signal, IBOC digital radio signal, Bluetooth radio signal and a broadcast cable signal.

6. The radio receiver of claim 1 wherein at least one of:

the analog front end, the digital clock generator, and the digital section, are implemented as part of a system on a chip integrated circuit.

7. A system on a chip integrated circuit (IC) comprising:

a first in-phase digital submodule;

a first quadrature phase digital submodule;

a second in-phase digital submodule;

a second quadrature phase digital submodule; and

a digital clock generator, operably coupled to the first in-phase digital submodule, the first quadrature phase digital submodule, the second in-phase digital submodule, and the second quadrature phase digital submodule, for generating a first in-phase digital clock signal having a plurality of first in-phase digital clock cycles over a predetermined period and a first quadrature phase digital clock signal having a plurality of first quadrature phase digital clock cycles over the predetermined period, wherein the plurality of first in-phase digital clock cycles are substantially interleaved with the plurality of first quadrature phase digital clock cycles over the predetermined period, wherein the digital clock generator generates a second in-phase digital clock signal having a plurality of second in-phase digital clock cycles over the predetermined period and a second quadrature phase digital clock signal having a plurality of second quadrature phase digital clock cycles over the predetermined period, and wherein the plurality of second in-phase digital clock cycles are substantially interleaved with the plurality of second quadrature phase digital clock cycles over the predetermined period;

wherein the first in-phase digital submodule and the first quadrature phase digital submodule are operable to produce at least one output signal based on at least one input signal.

8. The system on a chip integrated circuit (IC) of claim 7 wherein the plurality of first in-phase digital clock cycles are equal to the plurality of first quadrature phase digital clock cycles over the predetermined period.

9. The system on a chip integrated circuit (IC) of claim 7 wherein the digital. clock generator generates a base clock signal at a base clock frequency that varies based on a control signal and wherein the plurality of first in-phase digital clock cycles and the plurality of first quadrature phase digital clock cycles are substantially constant over the predetermined period.

10. The system on a chip integrated circuit (IC) of claim 7 wherein the digital clock generator substantially alternates between generating one or more of the plurality of first in-phase digital clock cycles with one or more of the plurality of first quadrature phase digital clock cycles over the predetermined period.

11. The system on a chip integrated circuit (IC) of claim 7 wherein the digital clock generator generates at least one of the plurality of first in-phase digital clock cycles in synchronism with at least one of the plurality of first quadrature phase digital clock cycles over the predetermined period.

12. A radio receiver comprising:

an analog front end for receiving a radio signal containing a selected one of a plurality of channel signals, and for converting the selected one of the plurality of channel signals into a digital signal that includes an in-phase signal and a quadrature phase signal;

a digital section, operably coupled to the analog front end, for converting the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channel signals, the digital section having a first in-phase digital submodule, a first quadrature phase digital submodule, a second in-phase digital submodule, and a second quadrature phase digital submodule; and

a digital clock generator, operably coupled to the first in-phase digital submodule and the first quadrature phase digital submodule, for generating a first in-phase digital clock signal having a plurality of first in-phase digital clock cycles over a predetermined period and a first quadrature phase digital clock signal having a plurality of first quadrature phase digital clock cycles over the predetermined period, wherein the plurality of first in-phase digital clock cycles are substantially interleaved with the plurality of first quadrature phase digital clock cycles over the predetermined period, wherein the digital clock generator generates a second in-phase digital clock signal having a plurality of second in-phase digital clock cycles over the predetermined period and a second quadrature phase digital clock signal having a plurality of second quadrature phase digital clock cycles over the predetermined period, and wherein the plurality of second in-phase digital clock cycles are substantially interleaved with the plurality of second quadrature phase digital clock cycles over the predetermined period.