System for linear amplitude modulation

• US 7,672,648 B1
• Filed: 06/27/2005
• Issued: 03/02/2010
• Est. Priority Date: 06/26/2004
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Quintic Holdings (NXP Semiconductors NV)
• Inventors: Farias, Naone, Baytekin, Burcin, Lo, Carrie, Groe, John
• Primary Examiner(s): Urban; Edward
• Assistant Examiner(s): Hannon; Christian A
• Application Number:
  US11/167,943
• Time in Patent Office: 1,709 Days
• Field of Search: 455/108, 455/109, 455/126, 455/127.1, 455/127.2, 455/127.3, 330/83, 330/98, 330/127, 330/200
• US Class Current: 455/127.2
• CPC Class Codes: H03C 1/06 Modifications of modulator to reduce distortion, e.g. by feedback, and clearly applicable to more than one type of modulator
• CPC Class Codes: H03F 1/0216 Continuous control
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/324 An amplitude modulator or demodulator being used in the amplifier circuit
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/435 A peak detection being used in a signal measuring circuit in a controlling circuit of an amplifier
• CPC Class Codes: H03F 2203/45362 the AAC comprising multiple transistors parallel coupled at their gates and drains only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/45085 Long tailed pairs H03F3/45112, H03F3/45139 take precedence
• CPC Class Codes: H03F 3/45098 PI types H03F3/45125, H03F3/45152 take precedence
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H04B 2001/0491 with frequency synthesizers, frequency converters or modulators

Abstract

System for linear amplitude modulation. Apparatus is provided for linear amplitude modulation of an amplifier. The apparatus includes a processing circuit that receives an amplitude modulation signal and produces one or more amplifier control signals that are coupled to the amplifier. The apparatus also includes a feedback circuit that generates a feedback signal from an output of the amplifier that is input to the processing circuit; and a network that controls a bias of the amplifier in response to the feedback signal to linearize the amplifier'"'"'s amplitude control.

Claims

1. Apparatus for linear amplitude modulation of a multi-stage amplifier, the apparatus comprising:

a processing circuit that receives an amplitude modulation signal and a transmit control signal and produces at a first output a first amplifier control signal to control a first stage of the multi-stage amplifier and at a second output a second amplifier control signal to control a second stage of the multi-stage amplifier;

a detector circuit coupled to the output of the multi-stage amplifier to generate, at an output, a signal representing the output of the multi-stage amplifier;

a summing circuit having a first input coupled to the second output of the processing circuit to receive the second amplifier control signal and a second input coupled to the output of the detector circuit; and

a network coupled to an output of the summing circuit to controls a bias or a gain signal of the multi-stage amplifier to linearize the amplifier'"'"'s amplitude control.

2. The Apparatus of claim 1 further comprising a first lowpass filter coupled to the first output of the processing circuit and a first stage of the multi-stage amplifier.

3. The Apparatus of claim 2 wherein the first stage is a VGA stage.

4. The Apparatus of claim 1 wherein the network comprises a lowpass filter and a bias circuit, wherein the lowpass filter is coupled to the output of the summing circuit and an input of the bias circuit and wherein an output of the bias circuit is coupled to a second stage of the multi-stage amplifier.

5. The Apparatus of claim 4 wherein the second stage of the multi-stage amplifier comprises a power amplifier stage.

6. The Apparatus of claim 1 wherein the processing circuit comprises a plurality of min and max circuits configured to generate the first amplifier control signal and the second amplifier control signal.

7. The Apparatus of claim 6 wherein the first amplifier control signal is designated VGA* and the second amplifier control signal is designated PA*, with VGA* generated in accordance with a relationship governed by:

VGA*=AM for AM<

(P2−

TX);

VGA*=P2+u(PA*) for (P2−

TX)>

=AM<

=(P1−

TX); and

VGA*=P2+u(Delta P2)+(AM−

P1) for AM>

(P1−

TX); and

wherein AM is a signal proportional to the amplitude modulation signal, P1 is a power level at which amplifier control through the bias network or voltage supply may be effected, P2 is the absolute lower limit of the amplifier'"'"'s modulation range, u is a scaling factor, and TX is the transmit output power level set by the transmit control signal.

8. The Apparatus of claim 6 wherein the second amplifier control signal is designated PA*, with PA* generated in accordance with a relationship governed by:

PA*=P2 for AM<

(P2−

TX)

PA*=AM+TX for (P2−

TX)>

=AM<

=(P1−

TX); and

PA*=P1 for AM>

(P1−

TX); and

wherein AM is a signal proportional to the amplitude modulation signal, P1 is a power level at which amplifier control through the bias network or voltage supply may be effected, P2 is the absolute lower limit of the amplifier'"'"'s modulation range, and TX is the transmit output power level set by the transmit control signal.

9. The Apparatus of claim 1 further comprising:

a duplicate lowpass filter coupled between a phase or frequency modulated input signal and a VCO coupled to the multi-stage amplifier, wherein the network comprises a lowpass filter, and wherein said duplicate lowpass filter is configured to match a set of filter characteristics of the lowpass filter.

10. The Apparatus of claim 1 further comprising:

an alignment circuit coupled to an input AM signal, an input PM or FM signal, the processing circuit and a VCO coupled to the multi-stage amplifier, wherein said amplitude alignment circuit is configured to delay the input AM signal or input PM or FM signal to compensate for time delays in the AM or PM or FM signal paths.

11. The Apparatus of claim 10 wherein the alignment circuit comprises a delay circuit configured to adjust the timing of the PM or FM signal.

12. The Apparatus of claim 11 wherein the delay circuit comprises a digital delay circuit.

13. The Apparatus of claim 10 wherein the alignment circuit comprises a digital delay circuit including a phase equalization filter coupled to the VCO and the FM or PM signal to match the delay of a filter in the network.

14. The Apparatus of claim 10 wherein the alignment circuit is configured to compensate for narrowband AM distortion.

15. The Apparatus of claim 14 wherein the alignment circuit is configured to compensate for narrowband AM distortion by:

receiving an original AM signal;

advancing the original AM signal; and

shifting the advanced signal towards a zero value to generate a compensated AM signal.

16. The Apparatus of claim 15 wherein the alignment circuit is further configured to rescale the compensated AM signal to approximate the original AM signal amplitude.

17. The Apparatus of claim 1 wherein the detector circuit is configured to provide a linear response signal to follow the envelope of the multi-stage amplifier output signal.

18. The Apparatus of claim 17 wherein the detector comprises:

an input capacitor coupled to a voltage signal, said voltage signal replicating the multi-stage amplifier output signal;

a resistor coupled to the capacitor and a bias voltage signal;

a transistor coupled to the input capacitor and resistor;

a diode coupled to the transistor; and

an output capacitor coupled to the transistor and diode to hold the peaks of the voltage signal.

19. The Apparatus of claim 18 wherein the transistor comprises a bipolar junction transistor (BJT).

20. The Apparatus of claim 18 wherein the transistor comprises a field effect transistor (FET).

21. The Apparatus of claim 17 further comprising a temperature compensated reference.

22. The Apparatus of claim 17 further comprising a transconductance circuit coupled to the detector circuit to translate a detector output voltage to an output current.

23. A method for amplitude modulating a multi-stage amplifier, comprising:

receiving, at a processing circuit, an amplitude modulation signal and a transmit control signal;

providing a first output from the processing circuit to a first stage of the multi-stage amplifier to selectively amplitude modulate the first stage;

providing a second output from the processing circuit to a summing circuit;

combining, in the summing circuit, the second output with an output of a detector circuit coupled to an output of the multi-stage amplifier to generate a summing circuit output; and

providing the summing circuit output to a network and the second stage to selectively amplitude modulate the second stage;

wherein the first output signal is designated VGA* and the second amplifier control signal is designated PA*, with VGA* generated in accordance with a relationship governed by;

VGA*=AM for AM<

(P2−

TX);

VGA*=P2+u(PA*) for (P2−

TX)>

=AM<

=(P1−

TX); and

VGA*=P2+u(Delta P2)+(AM−

P1) for AM>

(P1−

TX); and

wherein AM is a signal proportional to the amplitude modulation signal, P1 is a power level at which amplifier control through the bias network or voltage supply may be effected, P2 is the absolute lower limit of the amplifier'"'"'s modulation range, u is a scaling factor, and TX is the transmit output power level set by the transmit control signal.

24. The method of claim 23 further comprising aligning the amplitude modulation signal with a corresponding PM or FM signal to compensate for time delays in the AM or FM or PM signal paths.

25. The method of claim 24 wherein said aligning is performed by a delay circuit configured to delay the PM or FM signal.

26. The method of claim 25 further comprising applying the FM or PM signal to a phase equalization filter coupled to the VCO to match the delay of a filter in the network.

27. The method of claim 24 wherein said aligning is performed to compensate for narrowband AM distortion.

28. The method of claim 27 wherein the aligning includes:

receiving an original amplitude modulation signal;

advancing the original amplitude modulation signal to generate an advanced AM signal; and

shifting the advanced AM signal towards a zero value to generate a compensated AM signal.

29. The method of claim 28 wherein the aligning further includes rescaling the compensated AM signal to approximate the original AM signal amplitude.

30. The method of claim 23 wherein the detector circuit provides an output as a linear response signal generated to follow the envelope of the multi-stage amplifier output signal.

31. The method of claim 30 further comprising providing, in the detector circuit, a temperature compensated reference.

32. The method of claim 23 further comprising translating the detector output from a voltage to a current, and providing the current to the summing circuit.

33. A method for amplitude modulating a multi-stage amplifier, comprising:

receiving, at a processing circuit, an amplitude modulation signal and a transmit control signal;

providing a first output from the processing circuit to a first stage of the multi-stage amplifier to selectively amplitude modulate the first stage;

providing a second output from the processing circuit to a summing circuit;

combining, in the summing circuit, the second output with an output of a detector circuit coupled to an output of the multi-stage amplifier to generate a summing circuit output; and

providing the summing circuit output to a network and the second stage to selectively amplitude modulate the second stage;

wherein the second output signal is designated PA*, with PA* generated in accordance with a relationship governed by;

PA*=P2 for AM<

(P2−

TX)

PA*=AM+TX for (P2−

TX)>

=AM<

=(P1−

TX); and

PA*=P1 for AM>

(P1−

TX); and

wherein AM is a signal proportional to the amplitude modulation signal, P1 is a power level at which amplifier control through the bias network or voltage supply may be effected, P2 is the absolute lower limit of the amplifier'"'"'s modulation range, and TX is the transmit output power level set by the transmit control signal.

34. The method of claim 33 further comprising aligning the amplitude modulation signal with a corresponding PM or FM signal to compensate for time delays in the AM or FM or PM signal paths.

35. The method of claim 34 wherein said aligning is performed by a delay circuit configured to delay the PM or FM signal.

36. The method of claim 35 further comprising applying the FM or PM signal to a phase equalization filter coupled to the VCO to match the delay of a filter in the network.

37. The method of claim 34 wherein said aligning is performed to compensate for narrowband AM distortion.

38. The method of claim 37 wherein the aligning includes:

receiving an original amplitude modulation signal;

advancing the original amplitude modulation signal to generate an advanced AM signal; and

shifting the advanced AM signal towards a zero value to generate a compensated AM signal.

39. The method of claim 38 wherein the aligning further includes rescaling the compensated AM signal to approximate the original AM signal amplitude.

40. The method of claim 33 wherein the detector circuit provides an output as a linear response signal generated to follow the envelope of the multi-stage amplifier output signal.

41. The method of claim 40 further comprising providing, in the detector circuit, a temperature compensated reference.

42. The method of claim 33 further comprising translating the detector output from a voltage to a current, and providing the current to the summing circuit.