Differential data transfer for flash memory card
First Claim
1. A flash memory card comprising:
- a predetermined pin assignment based on a pin count of the flash memory card, the pin assignment including a plurality of dual-use pins that are used for legacy and differential signals;
a flash memory array;
a protocol controller for accessing the flash memory array; and
a differential datapath capable of converting an incoming differential signal into a status signal for the protocol controller and an incoming data signal for the protocol controller, and capable of converting a control signal from the protocol controller and an outgoing data signal from the protocol controller into an outgoing differential signal, wherein the differential datapath comprises;
a differential transceiver for converting the incoming differential signal into an incoming multipurpose serial signal, and for converting an outgoing multipurpose serial signal into the outgoing differential signal; and
a differential serial interface engine for converting the incoming multipurpose serial signal into at least one of the status signal and the incoming data signal, and for converting at least one of the control signal and the outgoing data signal into the outgoing multipurpose serial signal, wherein the differential serial interface engine comprises;
a synchronization detector for identifying a synchronization field in a first set of signals, and upon detection of the synchronization field, initiating packet reception by generating a start signal;
a write first-in-first-out (FIFO) memory for storing the first set of signals in response to the start signal and outputting at least one of the status signal and the incoming data signal;
a CRC (cyclic redundancy check) detector for performing a CRC check on the first set of signals in response to the start signal;
a command/data detector for determining whether the first set of signals are one of command signals and data signals in response to the start signal and providing that determination to the CRC detector;
a start-of-frame (SOF) detector for detecting SOF fields in the first set of signals in response to the start signal and, upon such detection, triggering a local clock generation; and
an end-of-packet (EOP) detector for detecting an EOP field in the first set of signals in response to the start signal and, upon such detection, issuing a stop signal to the write FIFO, the CRC detector, the command/data detector, and the SOF detector,wherein the flash memory card comprises one of a MultiMediaCard, a Secure-Digital card, a CompactFlash card, and a Memory Stick.
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Accused Products
Abstract
A flash memory card includes a differential datapath that enables communications between the flash memory card and a host device to be performed using differential signals. The differential datapath can translate between the differential signals and card-specific signals that control read/write operations to the memory array of the flash memory card. The card-specific signals can be standard MultiMediaCard, Secure-Digital card, Memory Stick, or CompactFlash card signals, among others. A host device that provides differential data transfer capability can include a similar differential datapath. By using differential data transfer rather than conventional clocked data transfer, overall data bandwidth between a flash memory card and a host device can be significantly increased, while simultaneously decreasing power consumption and pin requirements.
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Citations
9 Claims
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1. A flash memory card comprising:
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a predetermined pin assignment based on a pin count of the flash memory card, the pin assignment including a plurality of dual-use pins that are used for legacy and differential signals; a flash memory array; a protocol controller for accessing the flash memory array; and a differential datapath capable of converting an incoming differential signal into a status signal for the protocol controller and an incoming data signal for the protocol controller, and capable of converting a control signal from the protocol controller and an outgoing data signal from the protocol controller into an outgoing differential signal, wherein the differential datapath comprises; a differential transceiver for converting the incoming differential signal into an incoming multipurpose serial signal, and for converting an outgoing multipurpose serial signal into the outgoing differential signal; and a differential serial interface engine for converting the incoming multipurpose serial signal into at least one of the status signal and the incoming data signal, and for converting at least one of the control signal and the outgoing data signal into the outgoing multipurpose serial signal, wherein the differential serial interface engine comprises; a synchronization detector for identifying a synchronization field in a first set of signals, and upon detection of the synchronization field, initiating packet reception by generating a start signal; a write first-in-first-out (FIFO) memory for storing the first set of signals in response to the start signal and outputting at least one of the status signal and the incoming data signal; a CRC (cyclic redundancy check) detector for performing a CRC check on the first set of signals in response to the start signal; a command/data detector for determining whether the first set of signals are one of command signals and data signals in response to the start signal and providing that determination to the CRC detector; a start-of-frame (SOF) detector for detecting SOF fields in the first set of signals in response to the start signal and, upon such detection, triggering a local clock generation; and an end-of-packet (EOP) detector for detecting an EOP field in the first set of signals in response to the start signal and, upon such detection, issuing a stop signal to the write FIFO, the CRC detector, the command/data detector, and the SOF detector, wherein the flash memory card comprises one of a MultiMediaCard, a Secure-Digital card, a CompactFlash card, and a Memory Stick. - View Dependent Claims (2, 3, 4, 5)
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6. An electronic device comprising:
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a multi-personality bus interface system comprising; a connector slot; a plurality of protocol processors for providing a plurality of protocols; and a multiple-personality bus switch for connecting a selected protocol processor to the connector slot; a system processor for determining a capability of a flash memory card inserted into the connector slot and, based on the capability, selecting among any supported protocols of the plurality of protocols; and a host card adapter for interfacing with the flash memory card, the host card adapter comprising; a protocol controller; an application adapter for controlling the protocol controller, the application adapter providing a bridge between device-specific communications and card-specific communications; a differential datapath capable of converting an incoming differential signal into a status signal for the protocol controller and an incoming data signal for the protocol controller, and capable of converting a control signal from the protocol controller and an outgoing data signal from the protocol controller into an outgoing differential signal, wherein the differential datapath comprises; a differential transceiver for converting the incoming differential signal into an incoming multipurpose serial signal, and for converting an outgoing multipurpose serial signal into the outgoing differential signal; and a differential serial interface engine for converting the incoming multipurpose serial signal into at least one of the status signal and the incoming data signal, and for converting at least one of the control signal and the outgoing data signal into the outgoing multipurpose serial signal, wherein the differential serial interface engine comprises; a synchronization detector for identifying a synchronization field in a first set of signals, and upon detection of the synchronization field, initiating packet reception by generating a start signal; a read first-in-first-out (FIFO) memory for storing the first set of signals in response to the start signal and outputting at least one of the status signal and the incoming data signal; a CRC (cyclic redundancy check) detector for performing a CRC check on the first set of signals in response to the start signal; a command/data detector for determining whether the first set of signals are one of command signals and data signals in response to the start signal and providing that determination to the CRC detector; an end-of-packet (EOP) detector for detecting an EOP field in the first set of signals in response to the start signal and, upon such detection, issuing a stop signal to the read FIFO, the CRC detector, and the command/data detector; a write FIFO memory for storing at least one of the control signal and the outgoing data signals output by the protocol controller and outputting a second set of signals; a synchronization generator for generating a synchronization field for the second set of signals; a CRC generating circuit for generating a CRC field for the second set of signals; a command/data set circuit for determining whether the second set of signals are one of command signals and data signals and providing that determination to the CRC generating circuit; a start-of-frame (SOF) and an end-of-packet (EOP) generator for generating an SOF field and an EOP field for the second set of signals; a second converter for converting the second set of signals, the CRC field, and the EOP field, which are received in parallel, into an outgoing serial bitstream; and an encoder for applying non-return zero inverted (NRZI) encoding to the outgoing serial bitstream and outputting the outgoing multipurpose serial signal, wherein the flash memory card comprises one of a MultiMediaCard, a Secure-Digital card, a CompactFlash card. - View Dependent Claims (7, 8, 9)
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Specification