Arbitration for an embedded processor block core in an integrated circuit
First Claim
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1. A method for arbitration, comprising:
- associating master devices with a processor block core embedded in a host integrated circuit;
the master devices coupled to core logic of the host integrated circuit via a crossbar switch and a bridge;
the bridge being for access to and from the core logic and for access from and to the crossbar switch;
the crossbar switch and the bridge being part of the processor block core;
the crossbar switch including an arbiter;
selecting an arbitration protocol from among a plurality of arbitration protocols for use by the arbiter;
polling the master devices responsive to the arbitration protocol selected to identify a first pending transaction with a ready status of a first master device of the master devices;
sending the first pending transaction from the first master device to the arbiter; and
arbitrating by the arbiter the first pending transaction for access to the bridge using the arbitration protocol selected.
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Abstract
Arbitration for a processor block core is described. Master devices are associated with a processor block core embedded in a host integrated circuit (“IC”). The master devices are coupled to core logic of the host IC via a crossbar switch and a bridge, which are part of the processor block core. The crossbar switch includes an arbiter. An arbitration protocol is selected from among a plurality of arbitration protocols for use by the arbiter. Pending transactions having are polled for access to the bridge for arbitration using the arbitration protocol selected.
64 Citations
18 Claims
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1. A method for arbitration, comprising:
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associating master devices with a processor block core embedded in a host integrated circuit; the master devices coupled to core logic of the host integrated circuit via a crossbar switch and a bridge; the bridge being for access to and from the core logic and for access from and to the crossbar switch; the crossbar switch and the bridge being part of the processor block core; the crossbar switch including an arbiter; selecting an arbitration protocol from among a plurality of arbitration protocols for use by the arbiter; polling the master devices responsive to the arbitration protocol selected to identify a first pending transaction with a ready status of a first master device of the master devices; sending the first pending transaction from the first master device to the arbiter; and arbitrating by the arbiter the first pending transaction for access to the bridge using the arbitration protocol selected. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for arbitration, comprising:
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associating master devices with a processor block core embedded in a host integrated circuit; the master devices coupled to core logic of the host integrated circuit via a crossbar switch, a first bridge, and a second bridge; each of the first bridge and the second bridge being for access to and from the core logic and for access from and to the crossbar switch; the crossbar switch, the first bridge, and the second bridge being part of the processor block core; the crossbar switch including a first arbiter and a second arbiter respectively for access to the first bridge and the second bridge; the first arbiter and the second arbiter being independent of one another; selecting a first arbitration protocol and a second arbitration protocol from among a plurality of arbitration protocols respectively for use by the first arbiter and the second arbiter; the first arbitration protocol and the second arbitration protocol capable of being same or different from one another for respective use by the first arbiter and the second arbiter; and polling the master devices to identify a master device of the master devices having a pending transaction for either the first bridge or the second bridge. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification