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Arbitration for an embedded processor block core in an integrated circuit

  • US 7,673,087 B1
  • Filed: 03/27/2008
  • Issued: 03/02/2010
  • Est. Priority Date: 03/27/2008
  • Status: Active Grant
First Claim
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1. A method for arbitration, comprising:

  • associating master devices with a processor block core embedded in a host integrated circuit;

    the master devices coupled to core logic of the host integrated circuit via a crossbar switch and a bridge;

    the bridge being for access to and from the core logic and for access from and to the crossbar switch;

    the crossbar switch and the bridge being part of the processor block core;

    the crossbar switch including an arbiter;

    selecting an arbitration protocol from among a plurality of arbitration protocols for use by the arbiter;

    polling the master devices responsive to the arbitration protocol selected to identify a first pending transaction with a ready status of a first master device of the master devices;

    sending the first pending transaction from the first master device to the arbiter; and

    arbitrating by the arbiter the first pending transaction for access to the bridge using the arbitration protocol selected.

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