Method and system for maximum residency replacement of cache memory
First Claim
1. A method for replacing one of a plurality of set ways of a cache set in the event of a cache tag miss, comprising the steps of:
- selecting a victim way as the cache way that is to be replaced according to the position of said cache way on a FIFO listing of cache ways for use in the operation of a digital signal processor;
placing at the end of said cache set FIFO listing subsequent cache tag misses to said cache set reusing a victim way on a next cache tag miss;
preventing reuse of a victim way until initial allocation of said victim way avoids incoherency between the cache tag and said cache set;
preventing reuse of a victim way until initial allocation of said victim way completes by stalling response to a reuse request until such initial allocation of said victim way completes;
preventing reuse of a victim way until initial allocation of said victim way completes by replaying a reuse request until such initial allocation of said victim way completes.
1 Assignment
0 Petitions
Accused Products
Abstract
Techniques for use in CDMA-based products and services, including replacing cache memory allocation so as to maximize residency of a plurality of set ways following a tag-miss allocation. Herein, steps forming a first-in, first-out (FIFO) replacement listing of victim ways for the cache memory, wherein the depth of the FIFO replacement listing approximately equals the number of ways in the cache set. The method and system place a victim way on the FIFO replacement listing only in the event that a tag-miss results in a tag-miss allocation, the victim way is placed at the tail of the FIFO replacement listing after any previously selected victim way. Use of a victim way on the FIFO replacement listing is prevented in the event of an incomplete prior allocation of the victim way by, for example, stalling a reuse request until such initial allocation of the victim way completes or replaying a reuse request until such initial allocation of the victim way completes.
8 Citations
29 Claims
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1. A method for replacing one of a plurality of set ways of a cache set in the event of a cache tag miss, comprising the steps of:
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selecting a victim way as the cache way that is to be replaced according to the position of said cache way on a FIFO listing of cache ways for use in the operation of a digital signal processor; placing at the end of said cache set FIFO listing subsequent cache tag misses to said cache set reusing a victim way on a next cache tag miss; preventing reuse of a victim way until initial allocation of said victim way avoids incoherency between the cache tag and said cache set; preventing reuse of a victim way until initial allocation of said victim way completes by stalling response to a reuse request until such initial allocation of said victim way completes; preventing reuse of a victim way until initial allocation of said victim way completes by replaying a reuse request until such initial allocation of said victim way completes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A cache way replacement circuit for operation in association with a digital signal processor, said cache way replacement circuit for replacing one of a plurality of set ways of a cache set in the event of a cache tag miss and comprising:
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victim way selection circuitry for selecting a victim way as the cache way that is to be replaced according to the position of said cache way on a FIFO listing of cache ways for use in the operation of the digital signal processor; FIFO listing populating circuitry for placing at the end of said cache set FIFO listing subsequent cache tag misses to said cache set reusing a victim way on a next cache tag miss; cache way reuse hazard detection circuitry for preventing reuse of a victim way until initial allocation of said victim way avoids incoherency between the cache tag and said cache set, said cache way reuse hazard detection circuitry further for preventing reuse of a victim way until initial allocation of said victim way completes by stalling response to a reuse request until such initial allocation of said victim way completes and preventing reuse of a victim way until initial allocation of said victim way completes by replaying a reuse request until such initial allocation of said victim way completes. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A digital signal processor including means for replacing one of a plurality of set ways of a cache set in the event of a cache tag miss, the digital signal processor comprising:
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means for selecting a victim way as the cache way that is to be replaced according to the position of said cache way on a FIFO listing of cache ways for use in the operation of the digital signal processor; means for placing at the end of said cache set FIFO listing subsequent cache tag misses to said cache set reusing a victim way on a next cache tag miss; means for preventing reuse of a victim way until initial allocation of said victim way avoids incoherency between the cache tag and said cache set; means for preventing reuse of a victim way until initial allocation of said victim way completes by stalling response to a reuse request until such initial allocation of said victim way completes; and means for preventing reuse of a victim way until initial allocation of said victim way completes by replaying a reuse request until such initial allocation of said victim way completes. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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28. A computer usable storage medium having computer readable program code means embodied therein for processing instructions on a digital signal processor for replacing one of a plurality of set ways of a cache set in the event of a cache tag miss, said computer usable storage medium comprising:
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computer readable program code means for selecting a victim way as the cache way that is to be replaced according to the position of said cache way on a FIFO listing of cache ways for use in the operation of the digital signal processor; computer readable program code means for placing at the end of said cache set FIFO listing subsequent cache tag misses to said cache set reusing a victim way on a next cache tag miss; computer readable program code means for preventing reuse of a victim way until initial allocation of said victim way avoids incoherency between the cache tag and said cache set; computer readable program code means for preventing reuse of a victim way until initial allocation of said victim way completes by stalling response to a reuse request until such initial allocation of said victim way completes; computer readable program code means for preventing reuse of a victim way until initial allocation of said victim way completes by replaying a reuse request until such initial allocation of said victim way completes. - View Dependent Claims (29)
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Specification