Systems and methods for CPU repair

• US 7,673,171 B2
• Filed: 02/17/2006
• Issued: 03/02/2010
• Est. Priority Date: 02/18/2005
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Kuntz, Guy, Sedmak, Michael, Pomaranski, Ken, Barlow, Jeff, Brauch, Jeff, Joyal, Lacey, Hack, Stephen, Calkin, Howard, Gratias, Raymond
• Primary Examiner(s): DUNCAN, MARC M
• Application Number:
  US11/356,548
• Publication Number:
  US 20060230254A1
• Time in Patent Office: 1,474 Days
• Field of Search: 714/7, 714/8, 714/42, 714/710, 714/711
• US Class Current: 714/6.32
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Abstract

Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.

Claims

1. A method for repairing a processor comprising the steps of:

initializing and executing an operating system;

generating an operating system interrupt;

determining that an allocated cache element contained in the processor is faulty; and

swapping in a spare cache element contained in the processor for said faulty allocated cache element during said operating system interrupt.

2. The method of claim 1, further comprising the step of:

monitoring for a cache error while said operating system is executing; and

gathering and recording cache error information.

3. The method of claim 1, further comprising the step of:

determining whether said spare cache element is available if said allocated cache element is determined to be faulty during said operating system interrupt.

4. The method of claim 3, further comprising the step of:

de-allocating said processor if said spare cache element is not available during said operating system interrupt.

5. The method of claim 4, further comprising the step of:

swapping in a spare processor for said de-allocated processor during said operating system interrupt.

6. The method of claim 1, further comprising the step of:

reporting actions taken and updating cache configuration on a memory device.

7. A CPU cache element management system comprising:

at least one CPU having at least one allocated cache element and at least one non-allocated cache element;

an operating system handler operable to generate an operating system interrupt; and

cache management logic operable to determine whether allocated cache elements are faulty and operable to swap in said non-allocated cache elements for said allocated cache elements during said operating system interrupt.

8. The CPU cache element management system of claim 7, wherein said cache management logic is further operable to monitor cache errors and record cache error information in a memory.

9. The CPU cache element management system of claim 8, wherein said cache error information is stored in a non-volatile memory.

10. The CPU cache management system of claim 7, wherein said cache management logic is further operable to determine whether at least one non-allocated cache element is available if said allocated cache element is determined to be faulty during said operating system interrupt.

11. The CPU cache management system of claim 10, wherein said cache management logic is further operable to de-allocate said CPU if said at least one non-allocated cache element is not available during said operating system interrupt.

12. The CPU cache management system of claim 11, wherein said cache management logic is further operable to swap in a spare CPU for said de-allocated CPU during said operating system interrupt.

13. The CPU cache management system of claim 7, wherein said cache management logic is further operable to report cache management actions taken and update a cache configuration stored on a memory device.

14. A computer system comprising:

at least one CPU having at least one allocated cache element and at least one spare cache element;

an operating system handler operable to generate an operating system interrupt; and

cache management logic operable to determine whether said at least one allocated cache element is faulty and operable to swap in said at least one spare cache element for said faulty allocated cache element during said operating system interrupt.

15. The computer system of claim 14, wherein said cache management logic is further operable to monitor cache errors and record cache error information in a memory.

16. The computer system of claim 15, wherein said cache error information is stored in a non-volatile memory.

17. The computer system of claim 14, wherein said cache management logic is further operable to determine whether said at least one spare cache element is available if said allocated cache element is faulty during said operating system interrupt.

18. The computer system of claim 17, wherein said cache management logic is further operable to de-allocate said CPU if said at least one spare cache element is not available.

19. The computer system of claim 18, wherein said cache management logic is further operable to swap in a spare CPU for said de-allocated CPU.

20. The computer system of claim 14, wherein said cache management logic is further operable to report cache management actions taken and update a cache configuration on a memory device.

21. A method for repairing a computer system having an operating system comprising the steps of:

monitoring at least one cache element contained in a CPU for at least one cache error;

recording cache error information associated with said at least one cache error;

generating an operating system interrupt;

determining whether said at least one cache element is faulty based on said cache error information;

determining if at least one spare cache element contained in the CPU is available if said at least one cache element is faulty; and

swapping in said at least one spare cache element if said at least one spare cache element is available and said at least one cache element is faulty during said operating system interrupt.

22. The method of claim 21, wherein said at least one cache element is determined to be faulty if a total number of errors occurring from said at least one cache element exceeds a predetermined threshold.

23. The method of claim 22, wherein said predetermined threshold is based on a total number of errors occurring from said cache element over a predetermined time period.

24. The method of claim 21 further comprising the step of:

de-allocating said at least one CPU if said at least one spare cache element is not available.

25. The method of claim 24 further comprising the steps of:

determining whether a spare CPU is available; and

swapping in said spare CPU for said de-allocated CPU if said spare CPU is available.

26. The method of claim 21 further comprising the step of:

updating a cache configuration in a memory.

27. A processor comprising:

a plurality of first memory portions;

a plurality of second memory portions;

logic for determining whether a first memory portion contained in the processor is faulty; and

logic for replacing the faulty first memory portion with a second memory portion contained in the processor during an operating system interrupt.

28. The processor of claim 27 wherein the logic for determining whether a first memory portion is faulty comprises logic for monitoring errors associated the first memory portion.

29. The processor of claim 27 wherein the logic for determining whether a first memory portion is faulty comprises logic for comparing a number of errors associated with the first memory portion to a threshold value.

30. The processor of claim 27 wherein the logic for replacing the faulty first memory portion with a second memory portion comprises logic for determining if a second memory portion is available for use in the replacement.

31. The processor of claim 27 wherein the logic for replacing the faulty first memory portion with a second memory portion comprises logic for de-allocating the processor if a second memory portion is not available for use in the replacement.

32. A processor comprising:

a first cache means configured for high-speed information storage and retrieval from the processor;

a second cache means for high-speed information storage and retrieval;

means for determining whether any portion of the first cache means configured for high-speed information storage is faulty; and

means for replacing the faulty portion of the first cache means with at least a portion of the second cache means for high-speed information storage and retrieval during an operating system interrupt.

33. The processor of claim 32 wherein the means for determining comprises means for monitoring errors associated the first cache means.

34. The processor of claim 32 wherein the means for determining comprises means for comparing a number of errors associated with the first cache means to a threshold value.

35. The processor of claim 32 wherein the means for replacing comprises means for determining if any portion of the second cache means is available for use in the replacement.

36. The processor of claim 32 wherein the means for replacing comprises means for de-allocating the processor if no portion of the second cache means is available for use in the replacement.